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| REJ09B0348-0100 16 H8/38776 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Super Low Power Series H8/38776F H8/38776 H8/38775 H8/38774 H8/38773 All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev.1.00 Revision Date: Dec. 18, 2006 Rev. 1.00 Dec. 18, 2006 Page ii of xxii Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev. 1.00 Dec. 18, 2006 Page iii of xxii General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. Rev. 1.00 Dec. 18, 2006 Page iv of xxii How to Use This Manual 1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control functions, and peripheral functions, electrical characteristics of the device, and usage notes. When designing an application system that includes this LSI, take all points to note into account. Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes. The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised items. For details on the revised points, see the actual locations in the manual. The following documents have been prepared for the H8/38776 Group. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document. Document Type Data Sheet Hardware Manual Contents Document Title Document No. This manual Overview of hardware and electrical characteristics Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, and timing charts) and descriptions of operation Detailed descriptions of the CPU and instruction set Examples of applications and sample programs Preliminary report on the specifications of a product, document, etc. H8/38776 Group Hardware Manual Software Manual Application Note Renesas Technical Update H8/300H Series Software Manual REJ09B0213 The latest versions are available from our web site. Rev. 1.00 Dec. 18, 2006 Page v of xxii 2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (2) Register notation The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. (3) Number notation Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (4) Notation for active-low An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF (4) (2) 14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1) CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0. 14.3 Operation 14.3.1 Interval Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected. Rev. 0.50, 10/04, page 416 of 914 (3) Note: The bit names and sentences in the above figure are examples and have nothing to do with the contents of this manual. Rev. 1.00 Dec. 18, 2006 Page vi of xxii 3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. [Table of Bits] (1) Bit 15 14 13 to 11 10 9 (2) Bit Name - - ASID2 to ASID0 - - - (3) (4) Description Reserved These bits are always read as 0. Address Identifier These bits enable or disable the pin function. Reserved This bit is always read as 0. Reserved This bit is always read as 1. (5) Initial Value R/W 0 0 All 0 0 1 0 R R R/W R R Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (1) Bit Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. (2) Bit name Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "-". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (3) Initial value Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 -: The initial value is undefined (4) R/W For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: The bit or field is readable and writable. R/(W): The bit or field is readable and writable. However, writing is only performed to flag clearing. R: The bit or field is readable. "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. W: The bit or field is writable. (5) Description Describes the function of the bit or field and specifies the values for writing. Rev. 1.00 Dec. 18, 2006 Page vii of xxii 4. Description of Abbreviations The abbreviations used in this manual are listed below. * Abbreviations used in this manual Description Asynchronous communication interface adapter Bits per second Cyclic redundancy check Direct memory access Direct memory access controller Global System for Mobile Communications High impedance Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.) Input/output Infrared Data Association Least significant bit Most significant bit No connection Phase-locked loop Pulse width modulation Special function register Subscriber Identity Module Universal asynchronous receiver/transmitter Voltage-controlled oscillator Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Rev. 1.00 Dec. 18, 2006 Page viii of xxii Contents Section 1 Overview................................................................................................1 1.1 Features................................................................................................................................. 1 1.1.1 Application ........................................................................................................... 1 1.1.2 Overview of Specifications................................................................................... 2 List of Products..................................................................................................................... 6 Block Diagram...................................................................................................................... 7 Pin Assignment ..................................................................................................................... 8 Pin Functions ...................................................................................................................... 13 1.2 1.3 1.4 1.5 Section 2 CPU......................................................................................................19 2.1 2.2 Address Space and Memory Map ....................................................................................... 20 Register Configuration........................................................................................................ 21 2.2.1 General Registers................................................................................................ 22 2.2.2 Program Counter (PC) ........................................................................................ 23 2.2.3 Condition-Code Register (CCR)......................................................................... 23 Data Formats....................................................................................................................... 25 2.3.1 General Register Data Formats ........................................................................... 25 2.3.2 Memory Data Formats ........................................................................................ 27 Instruction Set ..................................................................................................................... 28 2.4.1 Table of Instructions Classified by Function ...................................................... 28 2.4.2 Basic Instruction Formats ................................................................................... 38 Addressing Modes and Effective Address Calculation....................................................... 39 2.5.1 Addressing Modes .............................................................................................. 39 2.5.2 Effective Address Calculation ............................................................................ 43 Basic Bus Cycle .................................................................................................................. 45 2.6.1 Access to On-Chip Memory (RAM, ROM)........................................................ 45 2.6.2 On-Chip Peripheral Modules .............................................................................. 46 CPU States .......................................................................................................................... 47 Usage Notes ........................................................................................................................ 48 2.8.1 Notes on Data Access to Empty Areas ............................................................... 48 2.8.2 EEPMOV Instruction.......................................................................................... 48 2.8.3 Bit-Manipulation Instruction .............................................................................. 49 2.3 2.4 2.5 2.6 2.7 2.8 Section 3 Exception Handling .............................................................................55 3.1 3.2 Exception Sources and Vector Address .............................................................................. 56 Reset ................................................................................................................................... 57 Rev. 1.00 Dec. 18, 2006 Page ix of xxii 3.3 3.4 3.5 3.2.1 Reset Exception Handling .................................................................................. 57 3.2.2 Interrupt Immediately after Reset ....................................................................... 58 Interrupts............................................................................................................................. 59 Stack Status after Exception Handling ............................................................................... 60 3.4.1 Interrupt Response Time..................................................................................... 61 Usage Notes ........................................................................................................................ 62 3.5.1 Notes on Stack Area Use .................................................................................... 62 3.5.2 Notes on Rewriting Port Mode Registers ........................................................... 63 3.5.3 Method for Clearing Interrupt Request Flags ..................................................... 66 Section 4 Interrupt Controller.............................................................................. 67 4.1 4.2 4.3 Features............................................................................................................................... 67 Input/Output Pins................................................................................................................ 68 Register Descriptions.......................................................................................................... 68 4.3.1 Interrupt Edge Select Register (IEGR) ............................................................... 69 4.3.2 Wakeup Edge Select Register (WEGR).............................................................. 70 4.3.3 Interrupt Enable Register 1 (IENR1) .................................................................. 71 4.3.4 Interrupt Enable Register 2 (IENR2) .................................................................. 72 4.3.5 Interrupt Request Register 1 (IRR1) ................................................................... 73 4.3.6 Interrupt Request Register 2 (IRR2) ................................................................... 74 4.3.7 Wakeup Interrupt Request Register (IWPR) ...................................................... 76 4.3.8 Interrupt Priority Registers A to E (IPRA to IPRE)............................................ 78 4.3.9 Interrupt Mask Register (INTM) ........................................................................ 79 Interrupt Sources................................................................................................................. 79 4.4.1 External Interrupts .............................................................................................. 79 4.4.2 Internal Interrupts ............................................................................................... 81 Interrupt Exception Handling Vector Table........................................................................ 81 Operation ............................................................................................................................ 84 4.6.1 Interrupt Exception Handling Sequence ............................................................. 86 4.6.2 Interrupt Response Times ................................................................................... 88 Usage Notes ........................................................................................................................ 89 4.7.1 Contention between Interrupt Generation and Disabling.................................... 89 4.7.2 Instructions that Disable Interrupts..................................................................... 90 4.7.3 Interrupts during Execution of EEPMOV Instruction ........................................ 90 4.7.4 IENR Clearing .................................................................................................... 90 4.4 4.5 4.6 4.7 Section 5 Clock Pulse Generators ....................................................................... 91 5.1 Register Description ........................................................................................................... 93 5.1.1 SUB32k Control Register (SUB32CR)............................................................... 93 5.1.2 Oscillator Control Register (OSCCR) ................................................................ 94 Rev. 1.00 Dec. 18, 2006 Page x of xxii 5.2 5.3 5.4 5.5 System Clock Generator ..................................................................................................... 95 5.2.1 Connecting a Crystal Resonator.......................................................................... 95 5.2.2 Connecting a Ceramic Resonator........................................................................ 95 5.2.3 External Clock Input Method.............................................................................. 96 5.2.4 On-Chip Oscillator Selection Method (Supported only by the Mask ROM Version) ..................................................... 96 Subclock Generator............................................................................................................. 97 5.3.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator......................................... 97 5.3.2 Pin Connection when not Using Subclock.......................................................... 98 5.3.3 How to Input External Clock .............................................................................. 98 Prescalers ............................................................................................................................ 99 5.4.1 Prescaler S .......................................................................................................... 99 Usage Notes ...................................................................................................................... 100 5.5.1 Note on Resonators........................................................................................... 100 5.5.2 Notes on Board Design ..................................................................................... 103 5.5.3 Definition of Oscillation Stabilization Wait Time ............................................ 103 5.5.4 Note on Subclock Stop State............................................................................. 105 5.5.5 Note on Using Power-On Reset ........................................................................ 105 Section 6 Power-Down Modes ..........................................................................107 6.1 Register Descriptions........................................................................................................ 108 6.1.1 System Control Register 1 (SYSCR1) .............................................................. 108 6.1.2 System Control Register 2 (SYSCR2) .............................................................. 110 6.1.3 Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2) ............................... 111 Mode Transitions and States of LSI.................................................................................. 113 6.2.1 Sleep Mode ....................................................................................................... 119 6.2.2 Standby Mode ................................................................................................... 119 6.2.3 Watch Mode...................................................................................................... 120 6.2.4 Subsleep Mode.................................................................................................. 120 6.2.5 Subactive Mode ................................................................................................ 121 6.2.6 Active (Medium-Speed) Mode ......................................................................... 121 Direct Transition ............................................................................................................... 122 6.3.1 Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode ..................................................................................... 123 6.3.2 Direct Transition from Active (High-Speed) Mode to Subactive Mode ........... 124 6.3.3 Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode........................................................................................... 124 6.3.4 Direct Transition from Active (Medium-Speed) Mode to Subactive Mode ..... 125 6.3.5 Direct Transition from Subactive Mode to Active (High-Speed) Mode........... 125 6.3.6 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode ..... 126 Rev. 1.00 Dec. 18, 2006 Page xi of xxii 6.2 6.3 6.4 6.5 6.3.7 Notes on External Input Signal Changes before/after Direct Transition........... 126 Module Standby Function................................................................................................. 127 Usage Notes ...................................................................................................................... 127 6.5.1 Standby Mode Transition and Pin States .......................................................... 127 6.5.2 Notes on External Input Signal Changes before/after Standby Mode............... 128 Section 7 ROM .................................................................................................. 131 7.1 7.2 Block Configuration ......................................................................................................... 132 Register Descriptions........................................................................................................ 134 7.2.1 Flash Memory Control Register 1 (FLMCR1).................................................. 134 7.2.2 Flash Memory Control Register 2 (FLMCR2).................................................. 135 7.2.3 Erase Block Register 1 (EBR1) ........................................................................ 136 7.2.4 Flash Memory Power Control Register (FLPWCR)......................................... 137 7.2.5 Flash Memory Enable Register (FENR)........................................................... 137 On-Board Programming Modes........................................................................................ 138 7.3.1 Boot Mode ........................................................................................................ 139 7.3.2 Programming/Erasing in User Program Mode.................................................. 141 Flash Memory Programming/Erasing............................................................................... 143 7.4.1 Program/Program-Verify .................................................................................. 143 7.4.2 Erase/Erase-Verify............................................................................................ 146 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory....................... 146 Program/Erase Protection ................................................................................................. 148 7.5.1 Hardware Protection ......................................................................................... 148 7.5.2 Software Protection........................................................................................... 148 7.5.3 Error Protection ................................................................................................ 148 Programmer Mode ............................................................................................................ 149 Power-Down States for Flash Memory............................................................................. 149 Notes on Setting Module Standby Mode .......................................................................... 150 7.3 7.4 7.5 7.6 7.7 7.8 Section 8 RAM .................................................................................................. 153 Section 9 I/O Ports............................................................................................. 155 9.1 Port 1................................................................................................................................. 155 9.1.1 Port Data Register 1 (PDR1) ............................................................................ 156 9.1.2 Port Control Register 1 (PCR1) ........................................................................ 156 9.1.3 Port Pull-Up Control Register 1 (PUCR1)........................................................ 157 9.1.4 Port Mode Register 1 (PMR1) .......................................................................... 157 9.1.5 Pin Functions .................................................................................................... 158 9.1.6 Input Pull-Up MOS........................................................................................... 163 Rev. 1.00 Dec. 18, 2006 Page xii of xxii 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Port 3................................................................................................................................. 164 9.2.1 Port Data Register 3 (PDR3)............................................................................. 164 9.2.2 Port Control Register 3 (PCR3) ........................................................................ 165 9.2.3 Port Pull-Up Control Register 3 (PUCR3)........................................................ 165 9.2.4 Port Mode Register 3 (PMR3) .......................................................................... 166 9.2.5 Pin Functions .................................................................................................... 166 9.2.6 Input Pull-Up MOS........................................................................................... 168 Port 4................................................................................................................................. 169 9.3.1 Port Data Register 4 (PDR4)............................................................................. 169 9.3.2 Port Control Register 4 (PCR4) ........................................................................ 170 9.3.3 Port Mode Register 4 (PMR4) .......................................................................... 171 9.3.4 Pin Functions .................................................................................................... 172 Port 5................................................................................................................................. 173 9.4.1 Port Data Register 5 (PDR5)............................................................................. 174 9.4.2 Port Control Register 5 (PCR5) ........................................................................ 174 9.4.3 Port Pull-Up Control Register 5 (PUCR5)........................................................ 175 9.4.4 Port Mode Register 5 (PMR5) .......................................................................... 175 9.4.5 Pin Functions .................................................................................................... 176 9.4.6 Input Pull-Up MOS........................................................................................... 177 Port 6................................................................................................................................. 177 9.5.1 Port Data Register 6 (PDR6)............................................................................. 178 9.5.2 Port Control Register 6 (PCR6) ........................................................................ 178 9.5.3 Port Pull-Up Control Register 6 (PUCR6)........................................................ 179 9.5.4 Pin Functions .................................................................................................... 179 9.5.5 Input Pull-Up MOS........................................................................................... 180 Port 7................................................................................................................................. 181 9.6.1 Port Data Register 7 (PDR7)............................................................................. 181 9.6.2 Port Control Register 7 (PCR7) ........................................................................ 182 9.6.3 Pin Functions .................................................................................................... 182 Port 8................................................................................................................................. 183 9.7.1 Port Data Register 8 (PDR8)............................................................................. 184 9.7.2 Port Control Register 8 (PCR8) ........................................................................ 184 9.7.3 Pin Functions .................................................................................................... 185 Port 9................................................................................................................................. 186 9.8.1 Port Data Register 9 (PDR9)............................................................................. 186 9.8.2 Port Control Register 9 (PCR9) ........................................................................ 187 9.8.3 Port Mode Register 9 (PMR9) .......................................................................... 187 9.8.4 Pin Functions .................................................................................................... 188 Port A................................................................................................................................ 189 9.9.1 Port Data Register A (PDRA)........................................................................... 189 Rev. 1.00 Dec. 18, 2006 Page xiii of xxii 9.10 9.11 9.12 9.9.2 Port Control Register A (PCRA) ...................................................................... 190 9.9.3 Pin Functions .................................................................................................... 191 Port B................................................................................................................................ 192 9.10.1 Port Data Register B (PDRB) ........................................................................... 192 9.10.2 Port Mode Register B (PMRB)......................................................................... 193 9.10.3 Pin Functions .................................................................................................... 194 Input/Output Data Inversion ............................................................................................. 196 9.11.1 Serial Port Control Register (SPCR)................................................................. 196 Usage Notes ...................................................................................................................... 198 9.12.1 How to Handle Unused Pin .............................................................................. 198 Section 10 Realtime Clock (RTC)..................................................................... 199 10.1 10.2 10.3 Features............................................................................................................................. 199 Input/Output Pin ............................................................................................................... 200 Register Descriptions........................................................................................................ 200 10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR) ......... 201 10.3.2 Minute Data Register (RMINDR) .................................................................... 201 10.3.3 Hour Data Register (RHRDR) .......................................................................... 202 10.3.4 Day-of-Week Data Register (RWKDR) ........................................................... 203 10.3.5 RTC Control Register 1 (RTCCR1) ................................................................. 204 10.3.6 RTC Control Register 2 (RTCCR2) ................................................................. 205 10.3.7 Clock Source Select Register (RTCCSR)......................................................... 206 10.3.8 RTC Interrupt Flag Register (RTCFLG) .......................................................... 207 Operation .......................................................................................................................... 208 10.4.1 Initial Settings of Registers after Power-On ..................................................... 208 10.4.2 Initial Setting Procedure ................................................................................... 208 10.4.3 Data Reading Procedure ................................................................................... 209 Interrupt Sources............................................................................................................... 210 Usage Notes ...................................................................................................................... 211 10.6.1 Note on Clock Count ........................................................................................ 211 10.6.2 Note on Use of Interrupts.................................................................................. 211 10.4 10.5 10.6 Section 11 Timer F ............................................................................................ 213 11.1 11.2 11.3 Features............................................................................................................................. 213 Input/Output Pins.............................................................................................................. 214 Register Descriptions........................................................................................................ 215 11.3.1 Timer Counters FH and FL (TCFH, TCFL) ..................................................... 215 11.3.2 Output Compare Registers FH and FL (OCRFH, OCRFL).............................. 216 11.3.3 Timer Control Register F (TCRF) .................................................................... 217 11.3.4 Timer Control/Status Register F (TCSRF) ....................................................... 218 Rev. 1.00 Dec. 18, 2006 Page xiv of xxii 11.4 11.5 11.6 Operation .......................................................................................................................... 220 11.4.1 Timer F Operation ............................................................................................ 220 11.4.2 TCF Increment Timing ..................................................................................... 221 11.4.3 TMOFH/TMOFL Output Timing ..................................................................... 222 11.4.4 TCF Clear Timing............................................................................................. 222 11.4.5 Timer Overflow Flag (OVF) Set Timing .......................................................... 222 11.4.6 Compare Match Flag Set Timing...................................................................... 223 Timer F Operating States .................................................................................................. 223 Usage Notes ...................................................................................................................... 224 11.6.1 16-Bit Timer Mode ........................................................................................... 224 11.6.2 8-Bit Timer Mode ............................................................................................. 224 11.6.3 Flag Clearing..................................................................................................... 225 11.6.4 Timer Counter (TCF) Read/Write..................................................................... 227 Section 12 16-Bit Timer Pulse Unit (TPU) .......................................................229 12.1 12.2 12.3 Features............................................................................................................................. 229 Input/Output Pins.............................................................................................................. 231 Register Descriptions........................................................................................................ 232 12.3.1 Timer Control Register (TCR).......................................................................... 233 12.3.2 Timer Mode Register (TMDR) ......................................................................... 235 12.3.3 Timer I/O Control Register (TIOR) .................................................................. 236 12.3.4 Timer Interrupt Enable Register (TIER) ........................................................... 241 12.3.5 Timer Status Register (TSR)............................................................................. 242 12.3.6 Timer Counter (TCNT)..................................................................................... 243 12.3.7 Timer General Register (TGR) ......................................................................... 243 12.3.8 Timer Start Register (TSTR) ............................................................................ 244 12.3.9 Timer Synchro Register (TSYR) ...................................................................... 245 Interface to CPU ............................................................................................................... 246 12.4.1 16-Bit Registers ................................................................................................ 246 12.4.2 8-Bit Registers .................................................................................................. 246 Operation .......................................................................................................................... 248 12.5.1 Basic Functions................................................................................................. 248 12.5.2 Synchronous Operation..................................................................................... 253 12.5.3 Operation with Cascaded Connection............................................................... 255 12.5.4 PWM Modes ..................................................................................................... 257 Interrupt Sources............................................................................................................... 262 Operation Timing.............................................................................................................. 263 12.7.1 Input/Output Timing ......................................................................................... 263 12.7.2 Interrupt Signal Timing..................................................................................... 266 12.4 12.5 12.6 12.7 Rev. 1.00 Dec. 18, 2006 Page xv of xxii 12.8 Usage Notes ...................................................................................................................... 268 12.8.1 Module Standby Function Setting .................................................................... 268 12.8.2 Input Clock Restrictions ................................................................................... 268 12.8.3 Caution on Period Setting ................................................................................. 269 12.8.4 Contention between TCNT Write and Clear Operation ................................... 269 12.8.5 Contention between TCNT Write and Increment Operation ............................ 270 12.8.6 Contention between TGR Write and Compare Match ...................................... 271 12.8.7 Contention between TGR Read and Input Capture........................................... 272 12.8.8 Contention between TGR Write and Input Capture.......................................... 273 12.8.9 Contention between Overflow and Counter Clearing....................................... 274 12.8.10 Contention between TCNT Write and Overflow .............................................. 275 12.8.11 Multiplexing of I/O Pins ................................................................................... 275 12.8.12 Interrupts when Module Standby Function is Used.......................................... 275 Section 13 Asynchronous Event Counter (AEC) .............................................. 277 13.1 13.2 13.3 Features............................................................................................................................. 277 Input/Output Pins.............................................................................................................. 279 Register Descriptions........................................................................................................ 279 13.3.1 Event Counter PWM Compare Register (ECPWCR)....................................... 280 13.3.2 Event Counter PWM Data Register (ECPWDR).............................................. 281 13.3.3 Input Pin Edge Select Register (AEGSR)......................................................... 282 13.3.4 Event Counter Control Register (ECCR).......................................................... 283 13.3.5 Event Counter Control/Status Register (ECCSR)............................................. 284 13.3.6 Event Counter H (ECH).................................................................................... 286 13.3.7 Event Counter L (ECL)..................................................................................... 286 Operation .......................................................................................................................... 287 13.4.1 16-Bit Counter Operation ................................................................................. 287 13.4.2 8-Bit Counter Operation ................................................................................... 288 13.4.3 IRQAEC Operation........................................................................................... 289 13.4.4 Event Counter PWM Operation........................................................................ 289 13.4.5 Operation of Clock Input Enable/Disable Function.......................................... 290 Operating States of Asynchronous Event Counter............................................................ 291 Usage Notes ...................................................................................................................... 292 13.4 13.5 13.6 Section 14 Watchdog Timer.............................................................................. 293 14.1 14.2 Features............................................................................................................................. 293 Register Descriptions........................................................................................................ 294 14.2.1 Timer Control/Status Register WD1 (TCSRWD1)........................................... 295 14.2.2 Timer Control/Status Register WD2 (TCSRWD2)........................................... 297 14.2.3 Timer Counter WD (TCWD)............................................................................ 299 Rev. 1.00 Dec. 18, 2006 Page xvi of xxii 14.3 14.4 14.5 14.2.4 Timer Mode Register WD (TMWD) ................................................................ 299 Operation .......................................................................................................................... 300 14.3.1 Watchdog Timer Mode ..................................................................................... 300 14.3.2 Interval Timer Mode ......................................................................................... 301 14.3.3 Timing of Overflow Flag (OVF) Setting .......................................................... 301 Interrupt ............................................................................................................................ 302 Usage Notes ...................................................................................................................... 302 14.5.1 Switching between Watchdog Timer Mode and Interval Timer Mode............. 302 14.5.2 Module Standby Mode Control......................................................................... 302 14.5.3 Clearing of WT/IT and IEOVF Bits in TCSRWD2.......................................... 302 Section 15 Serial Communication Interface 3 (SCI3, IrDA).............................305 15.1 15.2 15.3 Features............................................................................................................................. 305 Input/Output Pins.............................................................................................................. 309 Register Descriptions........................................................................................................ 309 15.3.1 Receive Shift Register (RSR) ........................................................................... 310 15.3.2 Receive Data Register (RDR) ........................................................................... 310 15.3.3 Transmit Shift Register (TSR) .......................................................................... 310 15.3.4 Transmit Data Register (TDR).......................................................................... 310 15.3.5 Serial Mode Register (SMR) ............................................................................ 311 15.3.6 Serial Control Register (SCR)........................................................................... 314 15.3.7 Serial Status Register (SSR) ............................................................................. 316 15.3.8 Bit Rate Register (BRR) ................................................................................... 319 15.3.9 Serial Port Control Register (SPCR)................................................................. 327 15.3.10 IrDA Control Register (IrCR) ........................................................................... 329 Operation in Asynchronous Mode .................................................................................... 330 15.4.1 Clock................................................................................................................. 331 15.4.2 SCI3 Initialization............................................................................................. 335 15.4.3 Data Transmission ............................................................................................ 336 15.4.4 Serial Data Reception ....................................................................................... 338 Operation in Clock Synchronous Mode............................................................................ 342 15.5.1 Clock................................................................................................................. 342 15.5.2 SCI3 Initialization............................................................................................. 342 15.5.3 Serial Data Transmission .................................................................................. 343 15.5.4 Serial Data Reception (Clock Synchronous Mode) .......................................... 345 15.5.5 Simultaneous Serial Data Transmission and Reception.................................... 347 IrDA Operation ................................................................................................................. 348 15.6.1 Transmission..................................................................................................... 348 15.6.2 Reception .......................................................................................................... 349 15.6.3 High-Level Pulse Width Selection.................................................................... 350 Rev. 1.00 Dec. 18, 2006 Page xvii of xxii 15.4 15.5 15.6 15.7 15.8 Interrupt Requests............................................................................................................. 351 Usage Notes ...................................................................................................................... 354 15.8.1 Break Detection and Processing ....................................................................... 354 15.8.2 Mark State and Break Sending ......................................................................... 354 15.8.3 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only) ..................................................................... 354 15.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ..................................................................................... 355 15.8.5 Note on Switching SCK31 (SCK32) Pin Function ........................................... 356 15.8.6 Relation between Writing to TDR and Bit TDRE ............................................ 356 15.8.7 Relation between RDR Reading and bit RDRF................................................ 357 15.8.8 Transmit and Receive Operations when Making State Transition.................... 357 15.8.9 Setting in Subactive or Subsleep Mode ............................................................ 358 15.8.10 Oscillator when Serial Communication Interface 3 is Used (Supported only by the Mask ROM Version) ................................................... 358 Section 16 Serial Communication Interface 4 (SCI4)....................................... 359 16.1 16.2 16.3 Features............................................................................................................................. 359 Input/Output Pins.............................................................................................................. 360 Register Descriptions........................................................................................................ 361 16.3.1 Serial Control Register 4 (SCR4) ..................................................................... 361 16.3.2 Serial Control/Status Register 4 (SCSR4) ........................................................ 364 16.3.3 Transmit Data Register 4 (TDR4)..................................................................... 367 16.3.4 Receive Data Register 4 (RDR4)...................................................................... 367 16.3.5 Shift Register 4 (SR4)....................................................................................... 367 Operation .......................................................................................................................... 368 16.4.1 Clock................................................................................................................. 368 16.4.2 Data Transfer Format........................................................................................ 368 16.4.3 Data Transmission/Reception ........................................................................... 369 16.4.4 Data Transmission ............................................................................................ 370 16.4.5 Data Reception.................................................................................................. 372 16.4.6 Simultaneous Data Transmission and Reception.............................................. 374 Interrupt Sources............................................................................................................... 375 Usage Notes ...................................................................................................................... 376 16.6.1 Relationship between Writing to TDR4 and TDRE ......................................... 376 16.6.2 Receive Error Flag and Transmission............................................................... 376 16.6.3 Relationship between Reading RDR4 and RDRF ............................................ 376 16.6.4 SCK4 Output Waveform when Internal Clock of /2 is Selected..................... 377 16.4 16.5 16.6 Rev. 1.00 Dec. 18, 2006 Page xviii of xxii Section 17 14-Bit PWM.....................................................................................379 17.1 17.2 17.3 Features............................................................................................................................. 379 Input/Output Pins.............................................................................................................. 380 Register Descriptions........................................................................................................ 380 17.3.1 PWM Control Register (PWCR)....................................................................... 380 17.3.2 PWM Data Register (PWDR) ........................................................................... 381 Operation .......................................................................................................................... 382 17.4.1 Setting for Pulse-Division Type PWM Operation ............................................ 382 17.4.2 How to Set Pulse-Division Type PWM ............................................................ 382 17.4.3 Operation of Pulse-Division Type PWM.......................................................... 383 17.4.4 Setting for Standard PWM Operation ............................................................... 384 PWM Operating States ..................................................................................................... 385 Usage Notes ...................................................................................................................... 385 17.6.1 Relation between Writing to PWDR and Updating of PWM Waveform ......... 385 17.4 17.5 17.6 Section 18 A/D Converter..................................................................................387 18.1 18.2 18.3 Features............................................................................................................................. 387 Input/Output Pins.............................................................................................................. 389 Register Descriptions........................................................................................................ 389 18.3.1 A/D Result Register (ADRR) ........................................................................... 389 18.3.2 A/D Mode Register (AMR) .............................................................................. 390 18.3.3 A/D Start Register (ADSR) .............................................................................. 391 Operation .......................................................................................................................... 391 18.4.1 A/D Conversion ................................................................................................ 391 18.4.2 External Trigger Input Timing.......................................................................... 392 18.4.3 Operating States of A/D Converter................................................................... 392 Example of Use................................................................................................................. 393 A/D Conversion Accuracy Definitions ............................................................................. 396 Usage Notes ...................................................................................................................... 398 18.7.1 Permissible Signal Source Impedance .............................................................. 398 18.7.2 Influences on Absolute Accuracy ..................................................................... 398 18.7.3 Usage Notes ...................................................................................................... 399 18.4 18.5 18.6 18.7 Section 19 I2C Bus Interface 2 (IIC2) ................................................................401 19.1 19.2 19.3 Features............................................................................................................................. 401 Input/Output Pins.............................................................................................................. 403 Register Descriptions........................................................................................................ 404 19.3.1 I2C Bus Control Register 1 (ICCR1)................................................................. 404 19.3.2 I2C Bus Control Register 2 (ICCR2)................................................................. 407 Rev. 1.00 Dec. 18, 2006 Page xix of xxii 19.4 19.5 19.6 19.7 19.3.3 I2C Bus Mode Register (ICMR)........................................................................ 409 19.3.4 I2C Bus Interrupt Enable Register (ICIER)....................................................... 411 19.3.5 I2C Bus Status Register (ICSR)......................................................................... 413 19.3.6 Slave Address Register (SAR).......................................................................... 415 19.3.7 I2C Bus Transmit Data Register (ICDRT) ........................................................ 416 19.3.8 I2C Bus Receive Data Register (ICDRR).......................................................... 416 19.3.9 I2C Bus Shift Register (ICDRS)........................................................................ 416 Operation .......................................................................................................................... 417 19.4.1 I2C Bus Format.................................................................................................. 417 19.4.2 Master Transmit Operation............................................................................... 418 19.4.3 Master Receive Operation ................................................................................ 420 19.4.4 Slave Transmit Operation ................................................................................. 423 19.4.5 Slave Receive Operation................................................................................... 425 19.4.6 Clock Synchronous Serial Format .................................................................... 427 19.4.7 Noise Canceler.................................................................................................. 430 19.4.8 Example of Use................................................................................................. 430 Interrupt Request .............................................................................................................. 435 Bit Synchronous Circuit.................................................................................................... 436 Usage Notes ...................................................................................................................... 437 Section 20 Power-On Reset Circuit................................................................... 439 20.1 20.2 Feature .............................................................................................................................. 439 Operation .......................................................................................................................... 440 20.2.1 Power-On Reset Circuit .................................................................................... 440 Section 21 Address Break ................................................................................. 443 21.1 Register Descriptions........................................................................................................ 444 21.1.1 Address Break Control Register 2 (ABRKCR2) .............................................. 444 21.1.2 Address Break Status Register 2 (ABRKSR2) ................................................. 446 21.1.3 Break Address Registers 2 (BAR2H, BAR2L)................................................. 446 21.1.4 Break Data Registers 2 (BDR2H, BDR2L) ...................................................... 446 Operation .......................................................................................................................... 447 Operating States of Address Break ................................................................................... 448 21.2 21.3 Section 22 List of Registers............................................................................... 449 22.1 22.2 22.3 Register Addresses (Address Order)................................................................................. 450 Register Bits ..................................................................................................................... 455 Register States in Each Operating Mode .......................................................................... 461 Rev. 1.00 Dec. 18, 2006 Page xx of xxii Section 23 Electrical Characteristics .................................................................467 23.1 23.2 Absolute Maximum Ratings for F-ZTAT Version ........................................................... 467 Electrical Characteristics for F-ZTAT Version................................................................. 468 23.2.1 Power Supply Voltage and Operating Range.................................................... 468 23.2.2 DC Characteristics ............................................................................................ 471 23.2.3 AC Characteristics ............................................................................................ 478 23.2.4 A/D Converter Characteristics .......................................................................... 481 23.2.5 Power-On Reset Circuit Characteristics............................................................ 483 23.2.6 Watchdog Timer Characteristics....................................................................... 483 23.2.7 Flash Memory Characteristics .......................................................................... 484 Absolute Maximum Ratings for Masked ROM Version .................................................. 486 Electrical Characteristics for Masked ROM Version........................................................ 487 23.4.1 Power Supply Voltage and Operating Range.................................................... 487 23.4.2 DC Characteristics ............................................................................................ 490 23.4.3 AC Characteristics ............................................................................................ 496 23.4.4 A/D Converter Characteristics .......................................................................... 501 23.4.5 Power-On Reset Circuit Characteristics............................................................ 503 23.4.6 Watchdog Timer Characteristics....................................................................... 504 Operation Timing.............................................................................................................. 504 Output Load Circuit .......................................................................................................... 507 Recommended Resonators................................................................................................ 508 Usage Note........................................................................................................................ 508 23.3 23.4 23.5 23.6 23.7 23.8 Appendix..............................................................................................................509 A. Instruction Set ................................................................................................................... 509 A.1 Instruction List...................................................................................................... 509 A.2 Operation Code Map............................................................................................. 524 A.3 Number of Execution States ................................................................................. 528 A.4 Combinations of Instructions and Addressing Modes .......................................... 539 I/O Ports............................................................................................................................ 540 B.1 I/O Port Block Diagrams ...................................................................................... 540 B.2 Port States in Each Operating State ...................................................................... 558 Product Code Lineup ........................................................................................................ 559 Package Dimensions ......................................................................................................... 561 B. C. D. Index ....................................................................................................................565 Rev. 1.00 Dec. 18, 2006 Page xxi of xxii Rev. 1.00 Dec. 18, 2006 Page xxii of xxii Section 1 Overview Section 1 Overview 1.1 Features Microcontrollers of the H8/38776 Group are CISC (complex instruction set computer) microcontrollers whose core is an H8/300H CPU, which has an internal 32-bit architecture. The H8/300H CPU provides upward compatibility with the H8/300 CPUs of other Renesas Technology-original microcontrollers. As peripheral functions, each LSI of the Group includes various timer functions that realize lowcost configurations for end systems. The power consumption of these modules can be kept down dynamically by power-down mode. 1.1.1 Application Examples of the applications of this LSI include motor control, power meter, and health equipment. Rev. 1.00 Dec. 18, 2006 Page 1 of 568 REJ09B0348-0100 Section 1 Overview 1.1.2 Overview of Specifications Table 1.1 lists the functions of H8/38776 Group products in outline. Table 1.1 Overview of Functions Module/ Function ROM RAM CPU CPU Description * * * * * * * ROM lineup: Flash memory version and masked Rom version ROM capacity: 24 k, 32 k, 40 k, 48 k, and 52 kbytes RAM capacity: 1 k, 2 k, and 3 kbytes 16-bit H8/300H CPU (CISC type) Upward compatibility for H8/300 CPU at object level Sixteen 16-bit general registers Eight addressing modes 64-kbyte address space Program: 64 kbytes available Data: 64 kbytes available * 62 basic instructions, classifiable as bit arithmetic and logic instructions, multiply and divide instructions, bit manipulation instructions, and others Minimum instruction execution time: 200 ns (for an ADD instruction while system clock = 10 MHz and VCC = 2.7 to 3.6 V) On-chip multiplier (16 x 16 32 bits) Normal mode Classification Memory * * Operating mode MCU operating mode Interrupt (source) Interrupt controller (INTC) * Mode: Single-chip mode * * * * * Low power consumption state (transition driven by the SLEEP instruction) Fourteen external interrupt pins (NMI, IRQAEC, IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0) 25 internal interrupt sources for flash memory version (24 sources for mask ROM version) Two interrupt control modes (specified by the interrupt control register) Independent vector addresses Rev. 1.00 Dec. 18, 2006 Page 2 of 568 REJ09B0348-0100 Section 1 Overview Classification Clock Module/ Function Description Two clock generation circuits available Separate clock signals are provided for each of functional modules Includes frequency division circuit, so the operating frequency is selectable Seven low-power-consumption modes: Active (medium speed) mode, Sleep (high speed or medium speed) mode, subactive mode, subsleep mode, standby mode, and watch mode 10-bit resolution x eight input channels Sample and hold function included Conversion time: 12.4 s per channel (with at 5-MHz operation) Two ways to start A/D conversion: software and external trigger Two channels Four conversion periods selectable Pulse division method for ripple reduction 8-bit timer Timer-base functionality: Seven interrupt periods (0.25 second to one week) are selectable Free running counter: Eight clock sources are selectable 16-bit timer (also can be used as two independent 8-bit timers) Five counter input clocks Output compare function supported Toggle output function supported two interrupt sources: Compare match and overflow 16 bits x two channels Counter-input clocks selectable for each channel Up to four pulse inputs and outputs Waveform output by compare match, input capture function, counter clear operation, simultaneous writing to and clearing of multiple timer counters by compare match and input capture possible, simultaneous input/output for registers possible by counter synchronous operation, PWM output with a desired duty cycle, and up to two-phase PWM output possible by combination with synchronous operation Cascaded operation Six interrupt sources Clock pulse * generator * (CPG) * * A/D converter A/D converter (ADC) * * * Timer * 14-bit PWM * * * * Realtime clock (RTC) * * * Timer F * * * * 16-bit timer * pulse unit * (TPU) * * * * Rev. 1.00 Dec. 18, 2006 Page 3 of 568 REJ09B0348-0100 Section 1 Overview Classification Timer Module/ Function Description 16-bit pulse timer (also can be used as two 8 bits x two channels) Can count asynchronously-input external events 8 bits x one channel (selectable from nine counter input clocks) Asynchrono * us event counter * (AEC) * Watchdog timer Watchdog timer (WDT) Serial interface Serial communications interface 3 (SCI3, IrDA) Two channels (for both asynchronous and clock synchronous serial communications modes) * Full-duplex communications capability * Select the desired bit rate * Six interrupt sources * IrDA transfer capability (SCI3_1) * Clock synchronous serial communications with eight-bit buffer Serial communicat * Eight clock sources ions * Full-duplex communications capability interface 4 * Four interrupt sources (SCI4) * Pins are used by the on-chip emulator when it is in use 2 * One channel I C bus interface * Continuous transmission and reception 2 (IIC2) * I C bus format and clock synchronous serial format are selectable Generates the internal reset signal when power is supplied, by Power-on reset circuit connecting an external capacitor Address break I/O ports * * * * * * * * Supports on-board program debugging Eight CMOS input-only pins 55 CMOS input/output pins Four large-current-drive pins (port 9) 26 pull-up resistors QFP-80: package code: FP-80A (package dimensions: 14 x 14 mm, pin pitch: 0.65 mm) TQFP-80: package code: TFP-80C (package dimensions: 12 x 12 mm, pin pitch: 0.5 mm) P-TFLGA-85: package code TLP-85V (package dimensions: 7 x 7 mm, pin pitch: 0.65 mm) * Package Rev. 1.00 Dec. 18, 2006 Page 4 of 568 REJ09B0348-0100 Section 1 Overview Classification Module/ Function Description * * * * * Operating frequency: 2 to 10 MHz Power supply voltage: Vcc = 1.8 to 3.6 V, Avcc = 1.8 to 3.6 V Supply current: 6.6 mA (typ.) (Vcc = 3.0 V, Avcc = 3.0 V, = 10 MHz) -20 to +75C (regular specifications) -40 to +85C (wide-range specifications) Operating frequency/ Power supply voltage Operating peripheral temperature (C) Rev. 1.00 Dec. 18, 2006 Page 5 of 568 REJ09B0348-0100 Section 1 Overview 1.2 List of Products Table 1.2 and figure 1.1 show the list of products and the structure of a product number, respectively. Table 1.2 List of Products Model HD64F38776 Product Group H8/38776 Group ROM 52 kbytes RAM 2 kbytes Package FP-80A, TFP-80C, TLP-85V Remarks Flash memory version HD64338776 HD64338775 HD64338774 HD64338773 48 kbytes 40 kbytes 32 kbytes 24 kbytes 2 kbytes 2 kbytes 1 kbyte 1 kbyte Mask ROM version Mask ROM version Mask ROM version Mask ROM version Product part no. HD 64 F 38776 Indicates the product-specific number. H8/38776 Group Indicates the type of ROM device. F: Flash memory 3: Masked ROM Indicates the product family classification H8 Family Indicates the microcontroller. Figure 1.1 How to Read the Product Name Code Rev. 1.00 Dec. 18, 2006 Page 6 of 568 REJ09B0348-0100 Section 1 Overview 1.3 Block Diagram X1 X2 OSC1 OSC2 Subclock generator System clock generator System clock on-chip generator*3 H8/300H CPU Vcc AVcc Vss Vss/AVss RES TEST/ADTRG NMI *2 P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P84 P85 P86 P87 P90/PWM1 P91/PWM2 P92/IRQ4 P93 PA0 PA1 PA2 PA3 P10/AEVH P11/AEVL P12/TIOCA1/TCLKA P13/TIOCB1/TCLKB P14/TIOCA2/TCLKC P15/TIOCB2 12 P16/SCK4 * * ROM Port 1 RAM Port 7 Timer pulse unit P30/SCK32/TMOW P31/RXD32/SDA P32/TXD32/SCL 12 P36/SI4 * * 12 P37/SO4 * * Watchdog timer Port 3 Power-on reset circuit Port 8 14-bit PWM1 14-bit PWM2 P40/SCK31/TMIF P41/RXD31/IrRXD/TMOFL P42/TXD31/IrTXD/TMOFH IRQAEC Port 4 10-bit A/D converter Realtime clock P60 P61 P62 P63 P64 P65 P66 P67 Address break Port 6 : Large current port (15 mA) Notes: 1. The SCI4 pins, such as SCK4, SI4, and SO4, are supported only by the F-ZTAT version. 2. The SCK4, SI4, SO4, and NMI pins are not available when the E7 or on-chip emulator debugger is used. These pins are not available as ports. 3. Supported only by the masked ROM version. Figure 1.2 Block Diagram of H8/38776 Group Rev. 1.00 Dec. 18, 2006 Page 7 of 568 REJ09B0348-0100 Port B P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5 P56/WKP6 P57/WKP7 I2C bus interface Port 5 SCI3_2 PB0/AN0/IRQ0 PB1/AN1/IRQ1 PB2/AN2/IRQ3 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 SCI3_1/IrDA SCI4*1 Port A Asynchronous event counter Timer F Port 9 Section 1 Overview 1.4 Pin Assignment P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P86 P87 PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 PB3/AN3 PB2/AN2/IRQ3 PB1/AN1/IRQ1 PB0/AN0/IRQ0 AVcc Vss/AVss IRQAEC P90/PWM1 P91/PWM2 P92/IRQ4 P93 P10/AEVH P11/AEVL P12/TIOCA1/TCLKA 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 FP-80A, TFP-80C (Top view) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P61 P60 P57/WKP7 P56/WKP6 P55/WKP5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 PA3 PA2 PA1 PA0 Vss Vss Vss NC NC Vcc Figure 1.3 Pin Assignment of H8/38776 Group (FP-80A, TFP-80C) Rev. 1.00 Dec. 18, 2006 Page 8 of 568 REJ09B0348-0100 P13/TIOCB1/TCLKB P14/TIOCA2/TCLKC P15/TIOCB2 P16/SCK4 P30/SCK32/TMOW P31/RXD32/SDA P32/TXD32/SCL P36/SI4 P37/SO4 X1 X2 Vss OSC2 OSC1 TEST/ADTRG RES NMI P40/SCK31/TMIF P41/RXD31/IrRXD/TMOFL P42/TXD31/IrTXD/TMOFH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Section 1 Overview A10 B10 C10 D10 E10 F10 G10 H10 J10 K10 A9 B9 C9 D9 E9 F9 G9 H9 J9 K9 A8 B8 C8 D8 E8 F8 G8 H8 J8 K8 A7 B7 C7 H7 J7 K7 A6 B6 C6 H6 J6 K6 TLP-85V (Top view) A5 B5 C5 H5 J5 K5 A4 B4 C4 D4 H4 J4 K4 A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 Note: For details on pin correspondence, refer to table 1.3. Figure 1.4 Pin Assignment of H8/38776 Group (TLP-85V) Rev. 1.00 Dec. 18, 2006 Page 9 of 568 REJ09B0348-0100 Section 1 Overview Table 1.3 TLP-85V Pin Correspondence Pin Name H8/38776 Group Pin Symbol (TLP-85V) B1 C1 B2 C2 D1 D3 D2 E1 E3 F2 E2 F3 G3 F1 G2 H2 G1 H3 J1 H1 K1 K2 K3 J2 J3 K4 H4 J4 K5 P13/TIOCB1/TCLKB P14/TIOCA2/TCLKC P15/TIOCB2 P16/SCK4 P30/SCK32/TMOW P31/RXD32/SDA P32/TXD32/SCL P36/SI4 P37/SO4 X1 X2 Vss OSC2 OSC1 TEST/ADTRG RES NMI P40/SCK31/TMIF P41/RXD31/IrRXD/TMOFL P42/TXD31/IrTXD/TMOFH NC Vcc NC NC Vss Vss Vss PA0 PA1 Rev. 1.00 Dec. 18, 2006 Page 10 of 568 REJ09B0348-0100 Section 1 Overview Pin Name H8/38776 Group PA2 PA3 P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5 P56/WKP6 P57/WKP7 P60 P61 NC P62 P63 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 Pin Symbol (TLP-85V) H5 J6 J5 H6 H7 K6 J7 J8 K7 H8 K9 K8 K10 J10 H10 J9 H9 G10 G8 G9 F10 F8 E9 F9 E8 D8 E10 D9 C9 D10 C8 Rev. 1.00 Dec. 18, 2006 Page 11 of 568 REJ09B0348-0100 Section 1 Overview Pin Name H8/38776 Group P84 P85 NC P86 P87 PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 PB3/AN3 PB2/AN2/IRQ3 PB1/AN1/IRQ1 PB0/AN0/IRQ0 AVcc Vss/AVss IRQAEC P90/PWM1 P91/PWM2 P92/IRQ4 P93 P10/AEVH P11/AEVL P12/TIOCA1/TCLKA NC NC Pin Symbol (TLP-85V) B10 C10 A10 A9 A8 B9 B8 A7 C7 B7 A6 C6 B5 B6 C5 C4 A5 B4 B3 A4 C3 A2 A3 A1 D4 Rev. 1.00 Dec. 18, 2006 Page 12 of 568 REJ09B0348-0100 Section 1 Overview 1.5 Table 1.4 Pin Functions Pin Functions Pin No. Type Symbol FP-80A, TFP-80C 21 TLP-85V K2 I/O Input Functions Power supply pins. Connect this pin to the system power supply. Ground pins. Connect this pin to the system power supply (0 V). Analog power supply pins for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. Ground pins for the A/D converter. Connect this pin to the system power supply (0 V). These pins are not used. Power Vcc supply pins Vss AVcc 12, 24 to 26, 72 F3, J3, K4, H4, Input (= AVss) C5 (= AVss) 71 B6 Input AVss 72 (= Vss) C5 (= Vss) Input NC 22, 23 K3, J2 Clock pins OSC1 OSC2 14 13 F1 G3 Input Output These pins connect with crystal or ceramic resonator for the system clock, or can be used to input an external clock. See section 5, Clock Pulse Generators, for a typical connection. X1 X2 10 11 F2 E2 Input Output These pins connect with a 32.768- or 38.4-kHz crystal resonator for the subclock. See section 5, Clock Pulse Generators, for a typical connection. Reset pins. The power-on reset circuit is incorporated. When externally driven low, the chip is reset. System control RES 16 H2 Input Rev. 1.00 Dec. 18, 2006 Page 13 of 568 REJ09B0348-0100 Section 1 Overview Pin No. Type System control Symbol TEST FP-80A, TFP-80C 15 TLP-85V G2 I/O Input Functions Test pins. Also used as the ADTRG pin. When this pin is not used as the ADTRG pin, users cannot use this pin. Connect this pin to Vss. When this pin is used as the ADTRG pin, see section 18.4.2, External Trigger Input Timing. NMI interrupt request pins. Non-maskable interrupt request input pin. IRQ0 IRQ1 IRQ3 IRQ4 IRQAEC 70 69 68 76 73 B5 C6 A6 B3 C4 Input Input Input Input Input Interrupt input pins for the asynchronous event counter. This pin enables the asynchronous event input. In the masked ROM version, this pin controls turning on/off the on-chip oscillator during a reset. WKP0 to WKP7 16-bit timer TIOCA1 pulse unit (TPU) TIOCB1 TIOCA2 31 to 38 J5, H6, H7, K6, J7, J8, K7, H8 A3 Input Wakeup interrupt request input pins. Can select the rising or falling edge. I/O Pins for the TGR1A input capture input or output compare output, or PWM output. Pins for the TGR1B input capture input. Pins for the TGR2A input capture input or output compare output, or PWM output. Pins for the TGR2B input capture input. External interrupt request input pins. Can select the rising or falling edge. Interrupt pins NMI 17 G1 Input 80 1 2 B1 C1 Input I/O TIOCB2 3 B2 Input Rev. 1.00 Dec. 18, 2006 Page 14 of 568 REJ09B0348-0100 Section 1 Overview Pin No. Type Symbol FP-80A, TFP-80C 80 1 2 18 19 TLP-85V A3 B1 C1 H3 J1 I/O Input Input Input Input Event input pins for input to the timer F counter. Functions External clock input pins. 16-bit timer TCLKA pulse unit TCLKB (TPU) TCLKC Timer F TMIF TMOFL Output Output pins for waveforms generated by the timer FL output compare function. Output Output pins for waveforms generated by the timer FH output compare function. Input Input Event input pins for input to the asynchronous event counter. TMOFH 20 H1 Asynchronous event counter (AEC) Realtime clock (RTC) AEVL AEVH 79 78 A2 C3 TMOW 5 D1 Output Divided clock output pins for the RTC. 14-bit PWM PWM1 PWM2 Serial SCK4 communication interface 4 (SCI4) SI4 (F-ZTAT version only) SO4 74 75 4 A5 B4 C2 Output Output pins for waveforms generated by the 14-bit PWM in PWM channels Output 1 and 2. I/O Transfer clock pins for SCI4 data transmission/reception. When the E7 or on-chip emulator debugger is used, this pin is not available. SCI4 data input pins. When the E7 or on-chip emulator debugger is used, this pin is not available. 8 E1 Input 9 E3 Output SCI4 data output pins. When the E7 or on-chip emulator debugger is used, this pin is not available. Rev. 1.00 Dec. 18, 2006 Page 15 of 568 REJ09B0348-0100 Section 1 Overview Pin No. Type Serial communication interface 3 (SCI3) Symbol SCK31 RXD31/ IrRXD TXD31/ IrTXD SCK32 RXD32 TXD32 A/D converter AN0 to AN2 FP-80A, TFP-80C 18 19 20 5 6 7 70 to 68 TLP-85V H3 J1 H1 D1 D3 D2 B5, C6, A6 I/O I/O Input Functions SCI3_1 clock I/O pins. SCI3_1 data input pins or data input pins for the IrDA format. Output SCI3_1 data output pins or data output pins for the IrDA format. I/O Input SCI3_2 clock I/O pins. SCI3_2 data input pins. Output SCI3_2 data output pins. Input Analog data input pins for the A/D converter. AN3 to AN7 ADTRG I C bus SDA interface 2 SCL (IIC2) I/O ports P10 to P12 P13 to P16 P30 to P32, P36, P37 P40 to P42 2 67 to 63 15 6 7 78 to 80 1 to 4 5 to 9 B7, C7, A7, B8, B9 G2 D3 D2 C3, A2, A3 B1, C1, B2, C2 Input Input I/O I/O I/O External trigger input pins for the A/D converter. IIC data I/O pins. IIC clock I/O pins. 7-bit I/O pins. Input or output can be designated for each bit by means of the port control register 1 (PCR1). 5-bit I/O pins. Input or output can be designated for each bit by means of the port control register 3 (PCR3). 3-bit I/O pins. Input or output can be designated for each bit by means of the port control register 4 (PCR4). 8-bit I/O pins. Input or output can be designated for each bit by means of the port control register 5 (PCR5). 8-bit I/O pins. Input or output can be designated for each bit by means of the port control register 6 (PCR6). D1, D3, D2, E1, I/O E3 H3, J1, H1 I/O 18 to 20 P50 to P57 31 to 38 J5, H6, H7, K6, J7, J8, K7, H8 K9, K8, J10, H10, J9, H9, G10, G8 I/O P60 to P67 39 to 46 I/O Rev. 1.00 Dec. 18, 2006 Page 16 of 568 REJ09B0348-0100 Section 1 Overview Pin No. Type I/O ports Symbol P70 to P77 FP-80A, TFP-80C 47 to 54 TLP-85V I/O Functions 8-bit I/O pins. Input or output can be designated for each bit by means of the port control register 7 (PCR7). 8-bit I/O pins. Input or output can be designated for each bit by means of the port control register 8 (PCR8). 4-bit I/O pins. Input or output can be designated for each bit by means of the port control register 9 (PCR9). 4-bit I/O pins. Input or output can be designated for each bit by means of the port control register A (PCRA). 8-bit input-only pins G9, F10, F8, E9, I/O F9, E8, D8, E10 D9, C9, D10, C8, I/O B10, C10, A9, A8 A5, B4, B3, A4 I/O P80 to P87 55 to 62 P90 to P93 74 to 77 PA0 to PA3 27 to 30 J4, K5, H5, J6 I/O PB0 to PB7 70 to 63 B5, C6, A6, B7, C7, A7, B8, B9 Input Rev. 1.00 Dec. 18, 2006 Page 17 of 568 REJ09B0348-0100 Section 1 Overview Rev. 1.00 Dec. 18, 2006 Page 18 of 568 REJ09B0348-0100 Section 2 CPU Section 2 CPU The microcontroller of the H8/38776 Group has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU, and supports only normal mode, which has a 64-kbyte address space. * Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added. * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit registers, or eight 32-bit registers * Sixty-two basic instructions 8/16/32-bit data transfer and arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 64-kbyte address space * High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract : 2 state 8 x 8-bit register-register multiply : 14 states 16 / 8-bit register-register divide : 14 states 16 x 16-bit register-register multiply : 22 states 32 / 16-bit register-register divide : 22 states Rev. 1.00 Dec. 18, 2006 Page 19 of 568 REJ09B0348-0100 Section 2 CPU * Power-down state Transition to power-down state by SLEEP instruction 2.1 Address Space and Memory Map The address space of the H8/38776 Group microcontrollers is 64 kbytes, which includes the program area and the data area. Figure 2.1 shows the memory map. HD64F38776 (Flash memory version) H'0000 H'0057 H'0058 Interrupt vector H'0000 H'0057 H'0058 HD64338776 (Masked ROM version) Interrupt vector On-chip ROM (48 kbytes) H'0000 H'0057 H'0058 H'9FFF H'A000 Not used H'F02F H'F030 H'F02F H'F030 HD64338775 (Masked ROM version) Interrupt vector On-chip ROM (40 kbytes) H'0000 H'0057 H'0058 H'7FFF H8000 HD64338774 (Masked ROM version) Interrupt vector On-chip ROM (32 kbytes) H'0000 H'0057 H'0058 H'5FFF H6000 HD64338773 (Masked ROM version) Interrupt vector On-chip ROM (24 kbytes) On-chip ROM (52 kbytes) H'CFFF H'D000 H'EFFF H'F000 H'BFFF H'C000 Not used H'F02F H'F030 Internal I/O registers Not used Not used H'F02F H'F030 Not used Internal I/O registers H'F09F H'F0A0 Internal I/O registers Internal I/O registers Internal I/O registers H'F09F H'F0A0 H'F09F H'F0A0 H'F09F H'F0A0 H'F09F H'F0A0 Not used Not used Not used Not used Not used H'F37F H'F380 H'F77F H'F780 On-chip RAM (2 kbytes) H'F77F H'F780 On-chip RAM (2 kbytes) H'FB7F H'FB80 On-chip RAM (1 kbytes) H'FB7F H'FB80 On-chip RAM (1 kbytes) On-chip RAM (3 kbytes) H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFFF H'FFFF H'FFFF H'FFFF H'FFFF Note: Area H'C000 to H'CFFF is used by the on-chip debugger, and is not available to the user. Figure 2.1 Memory Map Rev. 1.00 Dec. 18, 2006 Page 20 of 568 REJ09B0348-0100 Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR). General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 E0 E1 E2 E3 E4 E5 E6 E7 (SP) 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control Registers (CR) 23 PC 0 76543210 CCR I UI H U N Z V C [Legend] SP: PC: CCR: I: UI: Stack pointer Program counter Condition-code register Interrupt mask bit User bit H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Figure 2.2 CPU Registers Rev. 1.00 Dec. 18, 2006 Page 21 of 568 REJ09B0348-0100 Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. The usage of each register can be selected independently. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H) Figure 2.3 Usage of General Registers General register ER7 has the function of the stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the relationship between the stack pointer and the stack area. Rev. 1.00 Dec. 18, 2006 Page 22 of 568 REJ09B0348-0100 Section 2 CPU Empty area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence. 2.2.3 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. For the action of each instruction on the flag bits, see appendix A.1, Instruction List. Rev. 1.00 Dec. 18, 2006 Page 23 of 568 REJ09B0348-0100 Section 2 CPU Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. 6 UI Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. Rev. 1.00 Dec. 18, 2006 Page 24 of 568 REJ09B0348-0100 Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats Figure 2.5 shows the data formats in general registers. Data Type 1-bit data General Register RnH Data Format 7 0 Don't care 7 0 76 54 32 10 1-bit data RnL Don't care 76 54 32 10 7 4-bit BCD data RnH Upper 43 Lower 0 Don't care 7 4-bit BCD data RnL 43 Upper Lower 0 Don't care 7 Byte data RnH 0 Don't care MSB LSB 7 Byte data RnL 0 LSB Don't care MSB Figure 2.5 General Register Data Formats (1) Rev. 1.00 Dec. 18, 2006 Page 25 of 568 REJ09B0348-0100 Section 2 CPU Data Type Word data General Register Rn Data Format 15 0 Word data En 15 0 MSB LSB MSB LSB 16 15 0 Longword data ERn 31 MSB LSB [Legend] ERn: General register ER En: Rn: General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev. 1.00 Dec. 18, 2006 Page 26 of 568 REJ09B0348-0100 Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches. When ER7 (SP) is used as an address register to access the stack area, the operand size should be word or longword. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 Data Format 0 0 Byte data Address L MSB LSB Word data Address 2M Address 2M+1 MSB LSB Longword data Address 2N Address 2N+1 Address 2N+2 Address 2N+3 MSB LSB Figure 2.6 Memory Data Formats Rev. 1.00 Dec. 18, 2006 Page 27 of 568 REJ09B0348-0100 Section 2 CPU 2.4 2.4.1 Instruction Set Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined in table 2.1. Table 2.1 Symbol Rd Rs Rn ERn (EAd) (EAs) CCR N Z V C PC SP #IMM disp + - x / Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register or address register) Destination operand Source operand Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT (logical complement) Rev. 1.00 Dec. 18, 2006 Page 28 of 568 REJ09B0348-0100 Section 2 CPU Symbol :3/:8/:16/:24 Note: * Description 3-, 8-, 16-, or 24-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7). Table 2.2 Instruction MOV Data Transfer Instructions Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) Rd Cannot be used in this LSI. Rs (EAs) Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. MOVFPE MOVTPE POP B B W/L PUSH W/L Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Dec. 18, 2006 Page 29 of 568 REJ09B0348-0100 Section 2 CPU Table 2.3 Instruction ADD SUB Arithmetic Operations Instructions (1) Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU B B/W/L L B B/W MULXS B/W DIVXU B/W Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Dec. 18, 2006 Page 30 of 568 REJ09B0348-0100 Section 2 CPU Table 2.3 Instruction DIVXS Arithmetic Operations Instructions (2) Size* B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Dec. 18, 2006 Page 31 of 568 REJ09B0348-0100 Section 2 CPU Table 2.4 Instruction AND Logic Operations Instructions Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement (logical complement) of general register contents. OR B/W/L XOR B/W/L NOT B/W/L Note: * Refers to the operand size. B: Byte W: Word L: Longword Table 2.5 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Shift Instructions Size* B/W/L B/W/L B/W/L B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. Rd (shift) Rd Performs a logical shift on general register contents. Rd (rotate) Rd Rotates general register contents. Rd (rotate) Rd Rotates general register contents through the carry flag. Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Dec. 18, 2006 Page 32 of 568 REJ09B0348-0100 Section 2 CPU Table 2.6 Instruction BSET Bit Manipulation Instructions Size* B Function 1 ( BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B BXOR B BIXOR B Rev. 1.00 Dec. 18, 2006 Page 33 of 568 REJ09B0348-0100 Section 2 CPU Instruction BLD Size* B Function ( BILD B BST B BIST B Note: * Refers to the operand size. B: Byte Rev. 1.00 Dec. 18, 2006 Page 34 of 568 REJ09B0348-0100 Section 2 CPU Table 2.7 Instruction Bcc* Branch Instructions Size Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1 JMP BSR JSR RTS Note: * Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine Bcc is the general name for conditional branch instructions. Rev. 1.00 Dec. 18, 2006 Page 35 of 568 REJ09B0348-0100 Section 2 CPU Table 2.8 Instruction RTE SLEEP LDC System Control Instructions Size* B/W Function Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. CCR (EAd) Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access. CCR #IMM CCR Logically ANDs the CCR with immediate data. CCR #IMM CCR Logically ORs the CCR with immediate data. CCR #IMM CCR Logically XORs the CCR with immediate data. PC + 2 PC Only increments the program counter. STC B/W ANDC ORC XORC NOP Note: * B B B Refers to the operand size. B: Byte W: Word Rev. 1.00 Dec. 18, 2006 Page 36 of 568 REJ09B0348-0100 Section 2 CPU Table 2.9 Instruction EEPMOV.B Block Data Transfer Instructions Size Function if R4L 0 then Repeat @ER5+ @ER6+, R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+, R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W Rev. 1.00 Dec. 18, 2006 Page 37 of 568 REJ09B0348-0100 Section 2 CPU 2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows examples of instruction formats. (1) Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00). (4) Condition Field Specifies the branching condition of Bcc instructions. (1) Operation field only op (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. NOP, RTS, etc. (3) Operation field, register fields, and effective address extension op EA(disp) (4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:8 rn rm MOV.B @(d:16, Rn), Rm Figure 2.7 Instruction Formats Rev. 1.00 Dec. 18, 2006 Page 38 of 568 REJ09B0348-0100 Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing Modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode (@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.10 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:24,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 (1) Register DirectRn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. Rev. 1.00 Dec. 18, 2006 Page 39 of 568 REJ09B0348-0100 Section 2 CPU (2) Register Indirect@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. (3) Register Indirect with Displacement@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. A 16-bit displacement is sign-extended when added. (4) Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn * Register indirect with post-increment@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. * Register indirect with pre-decrement@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. (5) Absolute Address@aa:8, @aa:16, @aa:24 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space. The access ranges of absolute addresses for this LSI are those shown in table 2.11, because the upper 8 bits are ignored. Rev. 1.00 Dec. 18, 2006 Page 40 of 568 REJ09B0348-0100 Section 2 CPU Table 2.11 Absolute Address Access Ranges Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 24 bits (@aa:24) Access Range H'FF00 to H'FFFF H'0000 to H'FFFF H'0000 to H'FFFF (6) Immediate#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. (7) Program-Counter Relative@(d:8, PC) or @(d:16, PC) This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed in words, generating a 16-bit branch address. Figure 2.8 shows how to specify branch address for in memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF). Note that the first part of the address range is also the exception vector area. Rev. 1.00 Dec. 18, 2006 Page 41 of 568 REJ09B0348-0100 Section 2 CPU Specified by @aa:8 Branch address Figure 2.8 Branch Address Specification in Memory Indirect Mode Rev. 1.00 Dec. 18, 2006 Page 42 of 568 REJ09B0348-0100 Section 2 CPU 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format Register direct(Rn) Effective Address Calculation Effective Address (EA) Operand is general register contents. op 2 rm rn 31 General register contents Register indirect(@ERn) 0 23 0 op 3 r Register indirect with displacement @(d:16,ERn) or @(d:24,ERn) 31 General register contents 0 23 0 op r disp 31 Sign extension 0 disp 4 Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+ 31 General register contents 0 23 0 op r 31 1, 2, or 4 *Register indirect with pre-decrement @-ERn 0 General register contents 23 0 op r 1, 2, or 4 The value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size. Rev. 1.00 Dec. 18, 2006 Page 43 of 568 REJ09B0348-0100 Section 2 CPU Table 2.12 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Absolute address Effective Address Calculation Effective Address (EA) @aa:8 op abs 23 H'FFFF 87 0 @aa:16 op abs 23 16 15 0 Sign extension @aa:24 op abs 23 0 6 Immediate #xx:8/#xx:16/#xx:32 op IMM Operand is immediate data. 7 Program-counter relative @(d:8,PC) @(d:16,PC) 23 PC contents 0 op disp 23 Sign extension 0 disp 23 0 8 Memory indirect @@aa:8 23 op abs H'0000 15 87 abs 0 0 Memory contents 23 16 15 H'00 0 [Legend] r, rm,rn : op : disp : IMM : abs : Register field Operation field Displacement Immediate data Absolute address Rev. 1.00 Dec. 18, 2006 Page 44 of 568 REJ09B0348-0100 Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock () or a subclock (SUB). The period from a rising edge of or SUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.9 shows the on-chip memory access cycle. Bus cycle T1 state or SUB T2 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2.9 On-Chip Memory Access Cycle Rev. 1.00 Dec. 18, 2006 Page 45 of 568 REJ09B0348-0100 Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 22.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size. When a register with 8-bit data bus width is accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the same as that for on-chip memory. Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module. Bus cycle T1 state or SUB T2 state T3 state Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Address Read data Write data Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access) Rev. 1.00 Dec. 18, 2006 Page 46 of 568 REJ09B0348-0100 Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. For the program halt state, there are sleep (high-speed or medium-speed) mode, standby mode, watch mode, and subsleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes. For details on exception handling, refer to section 3, Exception Handling. CPU state Reset state The CPU is initialized Program execution state Active (high-speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium-speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock Program halt state A state in which the CPU operation is stopped to reduce power consumption Sleep (high-speed) mode Sleep (medium-speed) mode Standby mode Watch mode Subsleep mode Exception-handling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt Figure 2.11 CPU Operating States Rev. 1.00 Dec. 18, 2006 Page 47 of 568 REJ09B0348-0100 Power-down modes Section 2 CPU Reset cleared Reset state Reset occurs Exception-handling state Reset occurs Reset occurs Interrupt source Interrupt source Exceptionhandling complete Program halt state SLEEP instruction executed Program execution state Figure 2.12 State Transitions 2.8 2.8.1 Usage Notes Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user. When data is transferred from CPU to empty areas, the transferred data will be lost. This action may also cause the CPU to malfunction. When data is transferred from an empty area to CPU, the contents of the data cannot be guaranteed. 2.8.2 EEPMOV Instruction EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution). Rev. 1.00 Dec. 18, 2006 Page 48 of 568 REJ09B0348-0100 Section 2 CPU 2.8.3 Bit-Manipulation Instruction The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where two registers are assigned to the same address, or when a bit is directly manipulated for a port or a register containing a write-only bit, because this may rewrite data of a bit other than the bit to be manipulated. (1) Bit manipulation for two registers assigned to the same address Example 1: Bit manipulation for the timer load register and timer counter Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. When a bit-manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. Data is read in byte units. 2. The CPU sets or resets the bit to be manipulated with the bit-manipulation instruction. 3. The written data is written again in byte units to the timer load register. The timer is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register. Read Count clock Timer counter Reload Write Timer load register Internal data bus Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address Rev. 1.00 Dec. 18, 2006 Page 49 of 568 REJ09B0348-0100 Section 2 CPU Example 2: When the BSET instruction is executed for port 5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below. * Prior to executing BSET instruction P57 Input/output Pin state PCR5 PDR5 Input Low level 0 1 P56 Input High level 0 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output Low level 1 0 * BSET instruction executed instruction BSET #0, @PDR5 The BSET instruction is executed for port 5. * After executing BSET instruction P57 Input/output Pin state PCR5 PDR5 Input Low level 0 0 P56 Input High level 0 1 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output High level 1 1 * Description on operation 1. When the BSET instruction is executed, first the CPU reads port 5. Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input). P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a value of H'80, but the value read by the CPU is H'40. 2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41. Rev. 1.00 Dec. 18, 2006 Page 50 of 568 REJ09B0348-0100 Section 2 CPU 3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction. As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5. * Prior to executing BSET instruction MOV.B MOV.B MOV.B #H'80, R0L R0L, @RAM0 R0L, @PDR5 P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 1 P56 Input High level 0 0 0 The PDR5 value (H'80) is written to a work area in memory (RAM0) as well as to PDR5. P55 Output Low level 1 0 0 P54 Output Low level 1 0 0 P53 Output Low level 1 0 0 P52 Output Low level 1 0 0 P51 Output Low level 1 0 0 P50 Output Low level 1 0 0 * BSET instruction executed BSET #0, @RAM0 The BSET instruction is executed designating the PDR5 work area (RAM0). * After executing BSET instruction MOV.B MOV.B @RAM0, R0L R0L, @PDR5 P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 1 P56 Input High level 0 0 0 The work area (RAM0) value is written to PDR5. P55 Output Low level 1 0 0 P54 Output Low level 1 0 0 P53 Output Low level 1 0 0 P52 Output Low level 1 0 0 P51 Output Low level 1 0 0 P50 Output High level 1 1 1 Rev. 1.00 Dec. 18, 2006 Page 51 of 568 REJ09B0348-0100 Section 2 CPU (2) Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin. * Prior to executing BCLR instruction P57 Input/output Pin state PCR5 PDR5 Input Low level 0 1 P56 Input High level 0 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output Low level 1 0 * BCLR instruction executed BCLR #0, @PCR5 The BCLR instruction is executed for PCR5. * After executing BCLR instruction P57 Input/output Pin state PCR5 PDR5 Output Low level 1 1 P56 Output High level 1 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Input High level 0 0 * Description on operation 1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F. 2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. 3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends. As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent this problem, store a copy of the PDR5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PDR5. Rev. 1.00 Dec. 18, 2006 Page 52 of 568 REJ09B0348-0100 Section 2 CPU * Prior to executing BCLR instruction MOV.B MOV.B MOV.B #H'3F, R0L R0L, @RAM0 R0L, @PCR5 P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 0 P56 Input High level 0 0 0 The PCR5 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR5. P55 Output Low level 1 0 1 P54 Output Low level 1 0 1 P53 Output Low level 1 0 1 P52 Output Low level 1 0 1 P51 Output Low level 1 0 1 P50 Output Low level 1 0 1 * BCLR instruction executed BCLR #0, @RAM0 The BCLR instructions executed for the PCR5 work area (RAM0). * After executing BCLR instruction MOV.B MOV.B @RAM0, R0L R0L, @PCR5 P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 0 P56 Input High level 0 0 0 The work area (RAM0) value is written to PCR5. P55 Output Low level 1 0 1 P54 Output Low level 1 0 1 P53 Output Low level 1 0 1 P52 Output Low level 1 0 1 P51 Output Low level 1 0 1 P50 Output High level 0 0 0 Rev. 1.00 Dec. 18, 2006 Page 53 of 568 REJ09B0348-0100 Section 2 CPU Rev. 1.00 Dec. 18, 2006 Page 54 of 568 REJ09B0348-0100 Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset or interrupts. * Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin. * Interrupts External interrupts other than NMI and internal interrupts other than address break are masked by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued. Rev. 1.00 Dec. 18, 2006 Page 55 of 568 REJ09B0348-0100 Section 3 Exception Handling 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.1 Exception Sources and Vector Address Exception Sources RES, Watchdog Timer Break instructions Break interrupts (mode transition) NMI Break conditions satisfied Break conditions satisfied IRQ0 IRQ1 IRQAEC IRQ3 IRQ4 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 Internal interrupts* Note: * Vector Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 to 43 Vector Address H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0057 Low Priority High Source Origin Reset Reserved for system use Reserved for system use External interrupt Reserved for system use Address break External interrupts For details on the vector table of internal interrupts, refer to section 4.5, Interrupt Exception Handling Vector Table. Rev. 1.00 Dec. 18, 2006 Page 56 of 568 REJ09B0348-0100 Section 3 Exception Handling 3.2 Reset A reset has the highest exception priority. Table 3.2 shows the three sources that cause a reset. Table 3.2 RES pin Power-on reset circuit Interrupt Sources that Cause a Reset Description Low-level input Rising of the power-supply voltage (Vcc) For details, see section 20, Power-On Reset Circuit. Origin of Interrupt Source Watchdog timer Counter overflow For details, see section 14, Watchdog Timer. 3.2.1 Reset Exception Handling When a reset is generated, all processing halts and this LSI enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules. To ensure that this LSI be reset, the RES pin has to be held low for the oscillation stabilization time of the system clock oscillator either after power-on or when the system clock oscillator is halted. If the system clock oscillator is functioning, the RES pin has to be held low for the number of the tREL state as is specified by the electrical characteristics. When a reset source has been raised, this LSI starts reset exception handling as follows. 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized and the I bit in CCR is set to 1. 2. The reset exception handling vector address (H'0000 and H'0001) is read and transferred to the PC, and then program execution starts from the address indicated by the PC. The sequence of the reset exception handling caused by the reset pin is shown in figure 3.1. Rev. 1.00 Dec. 18, 2006 Page 57 of 568 REJ09B0348-0100 Section 3 Exception Handling Reset cleared Initial program instruction prefetch Vector fetch Internal processing RES Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) (2) (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction Figure 3.1 Reset Exception Handling Sequence 3.2.2 Interrupt Immediately after Reset Immediately after a reset, if an interrupt is accepted before the stack pointer (SP) is initialized, PC and CCR will not be pushed onto the stack correctly, resulting in program runaway. To prevent this, immediately after reset exception handling all interrupts are masked. For this reason, the initial program instruction is always executed immediately after a reset. This instruction should initialize the stack pointer (e.g. MOV.L #xx: 32, SP). Rev. 1.00 Dec. 18, 2006 Page 58 of 568 REJ09B0348-0100 Section 3 Exception Handling 3.3 Interrupts The interrupt sources include 14 external interrupts (NMI, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, and WKP7 to WKP0) and 26 internal interrupts (for the flash memory version) or 25 internal interrupts (for the masked ROM version) from on-chip peripheral modules. Figure 3.2 shows the interrupt sources and their numbers. The on-chip peripheral modules which require interrupt sources are the watchdog timer (WDT), address break, realtime clock (RTC), 16-bit timer pulse unit (TPU), asynchronous event counter (AEC), timer F, serial communication interface (SCI), and A/D converter. Interrupt vector addresses are allocated to individual sources. NMI is an interrupt with the highest priority and accepted at all times. Interrupts are controlled by the interrupt controller. The interrupt controller sets interrupts other than NMI to three mask levels in order to control multiple interrupts. The interrupt priority registers A to E (IPRA to IPRE) of the interrupt controller set the interrupt mask levels. For details on interrupts, see section 4, Interrupt Controller. NMI (1) IRQ0, IRQ1, IRQ3, IRQ4, and IRQAEC (5) WKP0 to WKP7 (8) WDT*1 (1) Address break (1) Realtime clock (8) Asynchronous event counter (1) 16-bit timer pulse unit (6) Timer F (2) SCI3 (2) SCI4*2 (1) A/D converter (1) SLEEP instruction execution (1) IIC bus (1) External interrupts Interrupts Internal interrupts Notes: ( ) indicates the source number. 1. When the WDT is used as an interval timer, an interrupt request is generated each time the counter overflows. 2. Available only for the F-ZTAT version. Figure 3.2 Interrupt Sources and their Numbers Rev. 1.00 Dec. 18, 2006 Page 59 of 568 REJ09B0348-0100 Section 3 Exception Handling 3.4 Stack Status after Exception Handling Figures 3.3 shows the stack after completion of interrupt exception handling. SP - 4 SP (R7) CCR CCR* PCH PCL Even address SP - 3 SP - 2 SP - 1 SP + 1 SP + 2 SP + 3 SP + 4 SP (R7) Stack area Prior to start of interrupt exception handling PC and CCR saved to stack After completion of interrupt exception handling [Legend] PCH : Upper 8 bits of program counter (PC) PCL : Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. 2. Register contents must always be saved and restored by word length, starting from an even-numbered address. * Ignored when returning from the interrupt handling routine. Figure 3.3 Stack Status after Exception Handling Rev. 1.00 Dec. 18, 2006 Page 60 of 568 REJ09B0348-0100 Section 3 Exception Handling 3.4.1 Interrupt Response Time Table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.3 Item Waiting time for completion of executing instruction* Saving of PC and CCR to stack Vector fetch Instruction fetch Internal processing Note: * Excluding EEPMOV instruction. Interrupt Wait States States 1 to 23 4 2 4 4 Total 15 to 37 Rev. 1.00 Dec. 18, 2006 Page 61 of 568 REJ09B0348-0100 Section 3 Exception Handling 3.5 3.5.1 Usage Notes Notes on Stack Area Use When word data is accessed in this LSI, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH.W Rn (MOV.W Rn, @-SP) or PUSH.L ERn (MOV.L ERn, @-SP) to save registers. Use POP.W Rn (or MOV.W @SP+, Rn) or POP.L ERn (or MOV.L @SP+, ERn) to restore registers: Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.4. SP SP PCH PC L SP R1L PC L H'FEFC H'FEFD H'FEFF BSR instruction SP set to H'FEFF MOV. B R1L, @-R7 Contents of PCH are lost Stack accessed beyond SP [Legend] PCH: Upper byte of program counter PCL: Lower byte of program counter R1L: General register R1L SP: Stack pointer Figure 3.4 Operation when Odd Address is Set in SP When CCR contents are saved to the stack during interrupt exception handling or restored when an RTE instruction is executed, this also takes place in word units. Both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to CCR while the odd address contents are ignored. Rev. 1.00 Dec. 18, 2006 Page 62 of 568 REJ09B0348-0100 Section 3 Exception Handling 3.5.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins and when the value of the ECPWME bit in AEGSR is rewritten to switch between selection and nonselection of IRQAEC, the following points should be observed. When a pin function is switched by rewriting a port mode register that controls an external interrupt pin (IRQ4, IRQ3, IRQ1, IRQ0, or WKP7 to WKP0), the interrupt request flag is set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear the interrupt request flag to 0 after switching the pin function. When the value of the ECPWME bit in AEGSR that sets selection or non-selection of IRQAEC is rewritten, the interrupt request flag may be set to 1, even if a valid edge has not arrived on the selected IRQAEC or IECPWM (PWM output for the AEC). Therefore, be sure to clear the interrupt request flag to 0 after switching the pin function. Table 3.4 shows the conditions under which interrupt request flags are set to 1 in this way. Rev. 1.00 Dec. 18, 2006 Page 63 of 568 REJ09B0348-0100 Section 3 Exception Handling Table 3.4 Conditions under which Interrupt Request Flag is Set to 1 Conditions When the IRQ4 bit in PMR9 is changed from 0 to 1 while the IRQ4 pin is low and the IEG4 bit in IEGR is 0. When the IRQ4 bit in PMR9 is changed from 1 to 0 while the IRQ4 pin is low and the IEG4 bit in IEGR is 1. IRRI3 When the IRQ3 bit in PMRB is changed from 0 to 1 while the IRQ3 pin is low and the IEG3 bit in IEGR is 0. When the IRQ3 bit in PMRB is changed from 1 to 0 while the IRQ3 pin is low and the IEG3 bit in IEGR is 1. IRREC2 When an edge as designated by the AIEGS1 and AIEGS0 bits in AEGSR is detected because the values of the IRQAEC pin and of IECPWM at switching are different (e.g., when the rising edge has been selected and the ECPWME bit in AEGSR is changed from 1 to 0 while the IRQAEC pin is low and IECPWM is 1). When the IRQ1 bit in PMRB is changed from 0 to 1 while the IRQ1 pin is low and the IEG1 bit in IEGR is 0. When the IRQ1 bit in PMRB is changed from 1 to 0 while the IRQ1 pin is low and the IEG1 bit in IEGR is 1. IRRI0 When the IRQ0 bit in PMRB is changed from 0 to 1 while the IRQ0 pin is low and the IEG0 bit in IEGR is 0. When the IRQ0 bit in PMRB is changed from 1 to 0 while the IRQ0 pin is low and the IEG0 bit in IEGR is 1. Interrupt Request Flags Set to 1 IRR1 IRRI4 IRRI1 IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 When the WKP7 bit in PMR5 is changed from 0 to 1 while the WKP7 pin is low. When the WKP6 bit in PMR5 is changed from 0 to 1 while the WKP6 pin is low. When the WKP5 bit in PMR5 is changed from 0 to 1 while the WKP5 pin is low. When the WKP4 bit in PMR5 is changed from 0 to 1 while the WKP4 pin is low. When the WKP3 bit in PMR5 is changed from 0 to 1 while the WKP3 pin is low. When the WKP2 bit in PMR5 is changed from 0 to 1 while the WKP2 pin is low. When the WKP1 bit in PMR5 is changed from 0 to 1 while the WKP1 pin is low. When the WKP0 bit in PMR5 is changed from 0 to 1 while the WKP0 pin is low. Rev. 1.00 Dec. 18, 2006 Page 64 of 568 REJ09B0348-0100 Section 3 Exception Handling Figure 3.5 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. This procedure also applies to AEGSR setting. When switching a pin function, mask the interrupt before setting the bit in the port mode register (or AEGSR). After accessing the port mode register (or AEGSR), execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag to 0 is executed immediately after the port mode register (or AEGSR) access without executing an instruction, the flag will not be cleared. An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.4 are not satisfied. However, the procedure in figure 3.5 is recommended because IECPWM is an internal signal and determining its value is complicated. Interrupts masked. (Another possibility is to disable the relevant interrupt in the interrupt enable register 1.) I bit in CCR 1 Set port mode register (or AEGSR) bit Execute NOP instruction Clear interrupt request flag to 0 After setting the port mode register (or AEGSR) bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0 I bit in CCR 0 Interrupt mask cleared Figure 3.5 Port Mode Register (or AEGSR) Setting and Interrupt Request Flag Clearing Procedure Rev. 1.00 Dec. 18, 2006 Page 65 of 568 REJ09B0348-0100 Section 3 Exception Handling 3.5.3 Method for Clearing Interrupt Request Flags Use the recommended method given below when clearing the flags in interrupt request registers (IRR1, IRR2, and IWPR). (1) Recommended method Use a single instruction to clear flags. The bit manipulation instruction and byte-size data transfer instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 in IRR1) are given below. BCLR #1, @IRR1:8 MOV.B R1L, @IRR1:8 (set the value of R1L to B'11111101) (2) Example of a malfunction When flags are cleared with multiple instructions, other flags might be cleared during execution of the instructions, even though they are currently set, and this will cause a malfunction. Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1 (bit 1 in IRR1). MOV.B @IRR1:8,R1L ......... IRRI0 = 0 at this time AND.B #B'11111101,R1L ..... Here, IRRI0 = 1 MOV.B R1L,@IRR1:8 ......... IRRI0 is cleared to 0 In the above example, it is assumed that an IRQ0 interrupt is generated while the AND.B instruction is executing. The IRQ0 interrupt is disabled because, although the original objective is clearing IRRI1, IRRI0 is also cleared. Rev. 1.00 Dec. 18, 2006 Page 66 of 568 REJ09B0348-0100 Section 4 Interrupt Controller Section 4 Interrupt Controller 4.1 Features This LSI controls interrupts by the interrupt controller. The interrupt controller has the following features. * Mask levels settable with IPR An interrupt priority register (IPR) is provided for setting interrupt mask levels. Three mask levels can be set for each module for all interrupts except an NMI and address break. * Interrupts can be enabled or disabled in three levels by the INTM1 and INTM0 bits in the interrupt mask register (INTM). * Fourteen external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising or falling edge sensing can be selected for NMI. Rising or falling edge sensing can be selected for IRQ0, IRQ1, IRQ3, IRQ4, and WKP0 to WKP7. Rising, falling, or both edge sensing can be selected for IRQAEC. A block diagram of the interrupt controller is shown in figure 4.1. NMI/IRQ/ WKP input External interrupt input Interrupt request Vector number CCR ............ IENR1 Internal interrupt source TPU, SCI, etc. Priority determination I INTM IPR [Legend] IENR1: IPR: CCR: INTM: IRQ enable register 1 Interrupt priority register Condition code register Interrupt mask register Figure 4.1 Block Diagram of Interrupt Controller Rev. 1.00 Dec. 18, 2006 Page 67 of 568 REJ09B0348-0100 Section 4 Interrupt Controller 4.2 Input/Output Pins Table 4.1 shows the pin configuration of the interrupt controller. Table 4.1 Name NMI IRQAEC IRQ4 IRQ3 IRQ1 IRQ0 WKP7 to WKP0 Pin Configuration I/O Input Input Input Input Input Input Input Maskable external interrupt pins Accepted at a rising or falling edge Function Nonmaskable external interrupt pin Rising or falling edge can be selected Maskable external interrupt pin Rising, falling, or both edges can be selected Maskable external interrupt pins Rising or falling edge can be selected 4.3 Register Descriptions The interrupt controller has the following registers. * * * * * * * * * * * * * Interrupt edge select register (IEGR) Wakeup edge select register (WEGR) Interrupt enable register 1 (IENR1) Interrupt enable register 2 (IENR2) Interrupt request register 1 (IRR1) Interrupt request register 2 (IRR2) Wakeup interrupt request register (IWPR) Interrupt priority register A (IPRA) Interrupt priority register B (IPRB) Interrupt priority register C (IPRC) Interrupt priority register D (IPRD) Interrupt priority register E (IPRE) Interrupt mask register (INTM) Rev. 1.00 Dec. 18, 2006 Page 68 of 568 REJ09B0348-0100 Section 4 Interrupt Controller 4.3.1 Interrupt Edge Select Register (IEGR) IEGR selects the sense of an edge that generates interrupt requests of the NMI, TMIF, ADTRG, IRQ4, IRQ3, IRQ1, and IRQ0 pins. Bit 7 Bit Name NMIEG Initial Value 0 R/W R/W Descriptions NMI Edge Select 0: Detects a falling edge of the NMI pin input 1: Detects a rising edge of the NMI pin input 6 TMIFEG 0 R/W TMIF Edge Select 0: Detects a falling edge of the TMIF pin input 1: Detects a rising edge of the TMIF pin input 5 ADTRGNEG 0 R/W ADTRG Edge Select 0: Detects a falling edge of the ADTRG pin input 1: Detects a rising edge of the ADTRG pin input 4 IEG4 0 R/W IRQ4 Edge Select 0: Detects a falling edge of the IRQ4 pin input 1: Detects a rising edge of the IRQ4 pin input 3 IEG3 0 R/W IRQ3 Edge Select 0: Detects a falling edge of the IRQ3 pin input 1: Detects a rising edge of the IRQ3 pin input 2 1 IEG1 0 R/W Reserved IRQ1 Edge Select 0: Detects a falling edge of the IRQ1 pin input 1: Detects a rising edge of the IRQ1 pin input 0 IEG0 0 R/W IRQ0 Edge Select 0: Detects a falling edge of the IRQ0 pin input 1: Detects a rising edge of the IRQ0 pin input Rev. 1.00 Dec. 18, 2006 Page 69 of 568 REJ09B0348-0100 Section 4 Interrupt Controller 4.3.2 Wakeup Edge Select Register (WEGR) WEGR selects the sense of an edge that generates interrupt requests of the WKP7 to WKP0 pins. Bit 7 Bit Name WKEGS7 Initial Value 0 R/W R/W Description WKP7 Edge Select 0: Detects a falling edge of the WKP7 pin input 1: Detects a rising edge of the WKP7 pin input 6 WKEGS6 0 R/W WKP6 Edge Select 0: Detects a falling edge of the WKP6 pin input 1: Detects a rising edge of the WKP6 pin input 5 WKEGS5 0 R/W WKP5 Edge Select 0: Detects a falling edge of the WKP5 pin input 1: Detects a rising edge of the WKP5 pin input 4 WKEGS4 0 R/W WKP4 Edge Select 0: Detects a falling edge of the WKP4 pin input 1: Detects a rising edge of the WKP4 pin input 3 WKEGS3 0 R/W WKP3 Edge Select 0: Detects a falling edge of the WKP3 pin input 1: Detects a rising edge of the WKP3 pin input 2 WKEGS2 0 R/W WKP2 Edge Select 0: Detects a falling edge of the WKP2 pin input 1: Detects a rising edge of the WKP2 pin input 1 WKEGS1 0 R/W WKP1 Edge Select 0: Detects a falling edge of the WKP1 pin input 1: Detects a rising edge of the WKP1 pin input 0 WKEGS0 0 R/W WKP0 Edge Select 0: Detects a falling edge of the WKP0 pin input 1: Detects a rising edge of the WKP0 pin input Rev. 1.00 Dec. 18, 2006 Page 70 of 568 REJ09B0348-0100 Section 4 Interrupt Controller 4.3.3 Interrupt Enable Register 1 (IENR1) IENR1 enables the RTC, WKP7 to WKP0, IRQ0, IRQ1, IRQ3, IRQ4, and IRQAEC interrupts. Bit 7 Bit Name IENRTC Initial Value 0 R/W R/W Description RTC Interrupt Request Enable The RTC interrupt request is enabled when this bit is set to 1. 6 5 IENWP 1 0 R/W R/W Reserved This bit is always read as 1. Wakeup Interrupt Request Enable The WKP7 to WKP0 interrupt requests are enabled when this bit is set to 1. 4 IEN4 0 R/W IRQ4 Interrupt Request Enable The IRQ4 interrupt request is enabled when this bit is set to 1. 3 IEN3 0 R/W IRQ3 Interrupt Request Enable The IRQ3 interrupt request is enabled when this bit is set to 1. 2 IENEC2 0 R/W IRQAEC Interrupt Request Enable The IRQAEC interrupt request is enabled when this bit is set to 1. 1 IEN1 0 R/W IRQ1 Interrupt Request Enable The IRQ1 interrupt request is enabled when this bit is set to 1. 0 IEN0 0 R/W IRQ0 Interrupt Request Enable The IRQ0 interrupt request is enabled when this bit is set to 1. Rev. 1.00 Dec. 18, 2006 Page 71 of 568 REJ09B0348-0100 Section 4 Interrupt Controller 4.3.4 Interrupt Enable Register 2 (IENR2) IENR2 enables the direct transition, A/D converter, timer F, and asynchronous event counter interrupts. Bit 7 Bit Name IENDT Initial Value 0 R/W R/W Description Direct Transition Interrupt Request Enable The direct transition interrupt request is enabled when this bit is set to 1. 6 IENAD 0 R/W A/D Converter Interrupt Request Enable The A/D converter interrupt request is enabled when this bit is set to 1. 5 4 3 -- -- IENTFH 0 1 0 R/W R/W R/W Reserved This bit is read/write enable reserved bit. Reserved This bit is always read as 1. Timer FH Interrupt Request Enable The timer FH interrupt request is enabled when this bit is set to 1. 2 IENTFL 0 R/W Timer FL Interrupt Request Enable The timer FL interrupt request is enabled when this bit is set to 1. 1 0 IENEC 1 0 R/W R/W Reserved This bit is always read as 1. Asynchronous Event Counter Interrupt Request Enable The asynchronous event counter interrupt request is enabled when this bit is set to 1. Rev. 1.00 Dec. 18, 2006 Page 72 of 568 REJ09B0348-0100 Section 4 Interrupt Controller 4.3.5 Interrupt Request Register 1 (IRR1) IRR1 indicates the IRQ0, IRQ1, IRQ3, IRQ4, and IRQAEC interrupt request status. Bit 7 to 5 4 Initial Bit Name Value IRRI4 All 1 0 R/W R/W R/W Description Reserved These bits are always read as 1. IRQ4 Interrupt Request Flag [Setting condition] When the IRQ4 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit 3 IRRI3 0 R/W IRQ3 Interrupt Request Flag [Setting condition] When the IRQ3 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit 2 IRREC2 0 R/W IRQAEC Interrupt Request Flag [Setting condition] When the IRQAEC pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit 1 IRRI1 0 R/W IRQ1 Interrupt Request Flag [Setting condition] When the IRQ1 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit Rev. 1.00 Dec. 18, 2006 Page 73 of 568 REJ09B0348-0100 Section 4 Interrupt Controller Bit 0 Initial Bit Name Value IRRI0 0 R/W R/W Description IRQ0 Interrupt Request Flag [Setting condition] When the IRQ0 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit 4.3.6 Interrupt Request Register 2 (IRR2) IRR2 indicates the interrupt request status of the direct transition, A/D converter, timer F, and asynchronous event counter. Bit 7 Bit Name IRRDT Initial Value 0 R/W R/W Description Direct Transition Interrupt Request Flag [Setting condition] When the SLEEP instruction is executed and direct transition is made while the DTON bit in SYSCR2 is set to 1 [Clearing condition] When 0 is written to this bit 6 IRRAD 0 R/W A/D Converter Interrupt Request Flag [Setting condition] When A/D conversion ends [Clearing condition] When 0 is written to this bit 5 4 -- 0 1 R R/W Reserved This bit is always read as 0. Reserved This bit is always read as 1. Rev. 1.00 Dec. 18, 2006 Page 74 of 568 REJ09B0348-0100 Section 4 Interrupt Controller Bit 3 Bit Name IRRTFH Initial Value 0 R/W R/W Description Timer FH Interrupt Request Flag [Setting condition] When the timer FH compare match or overflow occurs [Clearing condition] When 0 is written to this bit 2 IRRTFL 0 R/W Timer FL Interrupt Request Flag [Setting condition] When the timer FL compare match or overflow occurs [Clearing condition] When 0 is written to this bit 1 0 IRREC 1 0 R/W R/W Reserved This bit is always read as 1. Asynchronous Event Counter Interrupt Request Flag [Setting condition] When the asynchronous event counter overflows [Clearing condition] When 0 is written to this bit Rev. 1.00 Dec. 18, 2006 Page 75 of 568 REJ09B0348-0100 Section 4 Interrupt Controller 4.3.7 Wakeup Interrupt Request Register (IWPR) IWPR has the WKP7 to WKP0 interrupt request status flags. Bit 7 Bit Name IWPF7 Initial Value 0 R/W R/W Description WKP7 Interrupt Request Flag [Setting condition] When the WKP7 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit 6 IWPF6 0 R/W WKP6 Interrupt Request Flag [Setting condition] When the WKP6 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit 5 IWPF5 0 R/W WKP5 Interrupt Request Flag [Setting condition] When the WKP5 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit 4 IWPF4 0 R/W WKP4 Interrupt Request Flag [Setting condition] When the WKP4 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit 3 IWPF3 0 R/W WKP3 Interrupt Request Flag [Setting condition] When the WKP3 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit Rev. 1.00 Dec. 18, 2006 Page 76 of 568 REJ09B0348-0100 Section 4 Interrupt Controller Bit 2 Bit Name IWPF2 Initial Value 0 R/W R/W Description WKP2 Interrupt Request Flag [Setting condition] When the WKP2 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit 1 IWPF1 0 R/W WKP1 Interrupt Request Flag [Setting condition] When the WKP1 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit 0 IWPF0 0 R/W WKP0 Interrupt Request Flag [Setting condition] When the WKP0 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit Rev. 1.00 Dec. 18, 2006 Page 77 of 568 REJ09B0348-0100 Section 4 Interrupt Controller 4.3.8 Interrupt Priority Registers A to E (IPRA to IPRE) IPR sets mask levels (levels 2 to 0) for interrupts other than the NMI and address break. The correspondence between interrupt sources and IPR settings is shown in table 4.2. Setting a value in the range from H'0 to H'3 in the 2-bit groups of bits 7 and 6, 5 and 4, 3 and 2, and 1 and 0 sets the priority of the corresponding interrupt. Bits 3 to 0 in IPRE are reserved. Bit 7 6 Initial Bit Name Value IPRn7 IPRn6 0 0 R/W R/W R/W Description Set the mask levels of the corresponding interrupt source. 00: Mask level 0 (Lowest) 01: Mask level 1 1*: Mask level 2 (Highest) 5 4 IPRn5 IPRn4 0 0 R/W R/W Set the mask levels of the corresponding interrupt source. 00: Mask level 0 (Lowest) 01: Mask level 1 1*: Mask level 2 (Highest) 3 2 IPRn3 IPRn2 0 0 R/W R/W Set the mask levels of the corresponding interrupt source. 00: Mask level 0 (Lowest) 01: Mask level 1 1*: Mask level 2 (Highest) 1 0 IPRn1 IPRn0 0 0 R/W R/W Set the mask levels of the corresponding interrupt source. 00: Mask level 0 (Lowest) 01: Mask level 1 1*: Mask level 2 (Highest) [Legend] *: Don't care. n = A to E Rev. 1.00 Dec. 18, 2006 Page 78 of 568 REJ09B0348-0100 Section 4 Interrupt Controller 4.3.9 Interrupt Mask Register (INTM) INTM is an 8-bit readable/writable register that controls 3-level interrupt masking depending on the combination of the INTM0 and INTM1 bits. Bit 7 to 2 1 0 Bit Name INTM1 INTM0 Initial Value All 1 0 0 R/W R/W R/W R/W Description Reserved These bits are always read as 1. Set the interrupt mask level. 1*: Mask an interrupt with mask level 1 or less 01: Mask an interrupt with mask level 0 00: Accept all interrupts [Legend] *: Don't care. 4.4 4.4.1 Interrupt Sources External Interrupts There are 14 external interrupts: NMI, WKP7 to WKP0, IRQ4, IRQ3, IRQAEC, IRQ1, and IRQ0. (1) NMI Interrupt NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the state of the I bit in CCR. The NMIEG bit in IEGR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. (2) WKP7 to WKP0 Interrupts WKP7 to WKP0 interrupts are requested by the rising or falling edge input signals at the WKP7 to WKP0 pins. When the rising or falling edge is input while the WKP7 to WKP0 pin functions are selected by PMR5, the corresponding bit in IWPR is set to 1 and an interrupt request is generated. Clearing the IENWP bit in IENR1 to 0 disables the wakeup interrupt request to be accepted. Setting the I bit in CCR to 1 masks all interrupts. Rev. 1.00 Dec. 18, 2006 Page 79 of 568 REJ09B0348-0100 Section 4 Interrupt Controller When exception handling for the WKP7 to WKP0 interrupts is accepted, the I bit in CCR is set to 1. The interrupt mask level can be set by IPR. (3) IRQ4, IRQ3, IRQ1, and IRQ0 Interrupts IRQ4, IRQ3, IRQ1, and IRQ0 interrupts are requested by input signals at IRQ4, IRQ3, IRQ1, and IRQ0 pins. Using the IEG4, IEG3, IEG1, and IEG0 bits in IEGR, it is possible to select whether an interrupt is generated by a rising or falling edge at IRQ4, IRQ3, IRQ1, and IRQ0 pins. When the specified edge is input while the IRQ4, IRQ3, IRQ1, and IRQ0 pin functions are selected by PMRB and PMR9, the corresponding bit in IRR1 is set to 1 and an interrupt request is generated. Clearing the IEN4, IEN3, IEN1, and IEN0 bits in IENR1 to 0 disables the interrupt request to be accepted. Setting the I bit in CCR to 1 masks all interrupts. The interrupt mask level can be set by IPR. (4) IRQAEC Interrupts An IRQAEC interrupt is requested by an input signal at the IRQAEC pin or IECPWM (PWM output for the AEC). When the IRQAEC pin is used as an external interrupt pin, clear the ECPWME bit in AEGSR to 0. Using the AIEGS1 and AIEGS0 bits in AEGSR, it is possible to select whether an interrupt is generated by a rising edge, falling edge, or both edges. When the IENEC2 bit in IENR1 is set to 1 and the specified edge is input, the corresponding bit in IRR1 is set to 1 and an interrupt request is generated. When exception handling for the IRQAEC interrupt is accepted, the I bit in CCR is set to 1. The interrupt mask level can be set by IPR. Rev. 1.00 Dec. 18, 2006 Page 80 of 568 REJ09B0348-0100 Section 4 Interrupt Controller 4.4.2 Internal Interrupts Internal interrupts generated from the on-chip peripheral modules have the following features: * For each on-chip peripheral module, there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. Internal interrupts can be controlled independently. If an enable bit is set to 1, an interrupt request is sent to the interrupt controller. * The interrupt mask level can be set by IPR. 4.5 Interrupt Exception Handling Vector Table Table 4.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. Interrupt mask levels other than NMI and address break can be modified by IPR. Rev. 1.00 Dec. 18, 2006 Page 81 of 568 REJ09B0348-0100 Section 4 Interrupt Controller Table 4.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Name RES, Watchdog Timer NMI Break conditions satisfied IRQ0 IRQ1 IRQAEC IRQ3 IRQ4 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 Vector Number 0 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Vector Address H'0000 H'0006 H'000A H'000C H'000E H'0010 H'0012 H'0014 H'0016 H'0018 H'001A H'001C H'001E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 Low IPRB5, IPRB4 IPRB7, IPRB6 IPRA7, IPRA6 IPRA5, IPRA4 IPRA3, IPRA2 IPRA1, IPRA0 IPR Priority High Origin of Interrupt Source Reset NMI Address break External pins RTC 0.25-second overflow 0.5-second overflow Second periodic overflow Minute periodic overflow Hour periodic overflow Day-of-week periodic overflow Week periodic overflow Free-running overflow Rev. 1.00 Dec. 18, 2006 Page 82 of 568 REJ09B0348-0100 Section 4 Interrupt Controller Origin of Interrupt Source WDT AEC TPU_1 Vector Number 27 28 29 30 31 32 33 34 35 36 Name WDT overflow (interval timer) AEC overflow TG1A (TG1A input capture/compare match) TG1B (TG1B input capture/compare match) TCI1V (overflow 1) Vector Address H'0036 H'0038 H'003A H'003C H'003E H'0040 H'0042 H'0044 H'0046 H'0048 H'004A IPR IPRB3, IPRB2 IPRB1, IPRB0 IPRC7, IPRC6 Priority High TPU_2 TG2A (TG2A input capture/compare match) TG2B (TG2B input capture/compare match) TCI2V (overflow 2) IPRC5, IPRC4 Timer F Timer FL compare match Timer FL overflow Timer FH compare match Timer FH overflow IPRC3, IPRC2 SCI4* Receive data full/transmit 37 data empty Transmit end/receive error Transmit completion/transmit data empty Receive data full/overrun error Framing error/parity error Transmit completion/transmit data empty Receive data full/overrun error Framing error/parity error Transmit data empty/transmit end Receive data full/overrun error NACK detection Arbitration/overrun error A/D conversion end 38 IPRC1, IPRC0 SCI3_1 H'004C IPRD7, IPRD6 SCI3_2 39 H'004E IPRD5, IPRD4 IIC 40 H'0050 IPRD3, IPRD2 10-bit A/D 42 43 H'0054 H'0056 IPRE7, IPRE6 IPRE5, IPRE4 Low (SLEEP instruction Direct transition execution) Note: * Supported only by the F-ZTAT version. Rev. 1.00 Dec. 18, 2006 Page 83 of 568 REJ09B0348-0100 Section 4 Interrupt Controller 4.6 Operation NMI and address break interrupts are accepted at all times except in the reset state. In the case of IRQ interrupts, WKP interrupts, and on-chip peripheral module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 4.3 shows the interrupt control states. Figure 4.2 shows a flowchart of the interrupt acceptance operation. Four-level interrupt masking is controlled according to the combination of the I bit in CCR and the INTM1 and INTM0 bits in INTM. Table 4.3 CCR I 1 0 INTM1 * 1 0 0 Interrupt Control States INTM INTM0 * * 1 0 States All interrupts other than NMI and address break are masked. Interrupts with mask level 1 or less are masked. Interrupts with mask level 0 are masked. All interrupts are accepted. [Legend] *: Don't care. 1. If an interrupt source whose enable bit is set to 1 occurs, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt mask levels set in IPR is selected, and lower-priority interrupt requests are held pending. If interrupt requests with the same priority are generated, the interrupt request with the highest priority according to table 4.2 is selected. 3. Control of interrupts is performed referencing the INTM1 and INTM0 bits in INTM and the I bit in CCR as follows: a. The interrupt request is held pending when the I bit is set to 1. b. When the I bit is cleared to 0 and INTM1 bit is set to 1, interrupts with mask level 1 or less are held pending. c. When the I bit is cleared to 0, INTM1 bit is cleared to 0, and INTM0 bit is set to 1, interrupt requests with mask level 0 are held pending. d. When the I bit, INTM1 bit, and INTM0 bit are all cleared to 0, all interrupt requests are accepted. Rev. 1.00 Dec. 18, 2006 Page 84 of 568 REJ09B0348-0100 Section 4 Interrupt Controller 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. PC and CCR are saved to the stack area by interrupt exception handling. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI and address break. 7. The CPU generates a vector address for the accepted interrupt and starts interrupt handling by reading the interrupt routine start address in the vector table. Program execution state Interrupt generated? Yes Yes NMI or address break? No No No Level 2 interrupt? Yes Level 1 interrupt? No No I = 0? Yes I = 0? No No Yes INTM1 = 0? INTM0 = 0? I = 0? Yes Yes No INTM1 = 0? No Yes Yes Save PC and CCR Hold pending I Read vector address Branch to interrupt handling routine Figure 4.2 Flowchart of Procedure Up to Interrupt Acceptance Rev. 1.00 Dec. 18, 2006 Page 85 of 568 REJ09B0348-0100 1 Section 4 Interrupt Controller 4.6.1 Interrupt Exception Handling Sequence Figure 4.3 shows the interrupt exception handling sequence. The example shown is for the case where the program area and stack area are in external memory with 16-bit and 2-state access space. Rev. 1.00 Dec. 18, 2006 Page 86 of 568 REJ09B0348-0100 Interrupt accepted Instruction prefetch Stack Interrupt level determination Wait for end of instruction Internal processing Vector fetch Internal processing Instruction prefetch of interrupt handling routine Interrupt request signal Address bus (1) (3) (5) (7) (9) (11) (12) RD HWR, LWR High D15 to D0 (2) (4) (6) (8) (10) (13) (1): Instruction prefetch address (Not executed. This is the contents of the saved PC and the return address.) (9)(11): Vector address (10): (12): (13): Interrupt handling routine start address (Vector address contents) Interrupt handling routine start address ((12) = (10)) First instruction of interrupt handling rou Figure 4.3 Interrupt Exception Handling Sequence Instruction prefetch address (Not executed.) SP-2 SP-4 (2)(4): Instruction code (Not executed.) (3): (5): (7): Section 4 Interrupt Controller Rev. 1.00 Dec. 18, 2006 Page 87 of 568 REJ09B0348-0100 (6)(8): Saved PC and saved CCR Section 4 Interrupt Controller 4.6.2 Interrupt Response Times Table 4.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. Table 4.4 No. 1 2 3 4 5 6 Interrupt Response Times (States) Number of States 1 or 2*1 1 to 23 4 2 2 Execution Status Interrupt priority determination Maximum number of wait states until executing instruction ends PC, CCR stack Vector fetch Instruction fetch* 3 4 4 18 to 41 Internal processing* Total Notes: 1. One state in case of an internal interrupt. 2. Prefetch after interrupt acceptance and interrupt handling routine prefetch. 3. Internal processing after interrupt acceptance and internal processing after vector fetch. Rev. 1.00 Dec. 18, 2006 Page 88 of 568 REJ09B0348-0100 Section 4 Interrupt Controller 4.7 4.7.1 Usage Notes Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request with higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 4.4 shows an example in which the TGIEA bit in TIER of the 16-bit timer pulse unit (TPU) is cleared to 0. TIER write cycle by CPU TGIA exception handling Internal address bus Internal write signal TIER address TGIEA TGIA TGIA interrupt signal Figure 4.4 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. Rev. 1.00 Dec. 18, 2006 Page 89 of 568 REJ09B0348-0100 Section 4 Interrupt Controller 4.7.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. When an interrupt request is generated, an interrupt is requested to the CPU after the interrupt controller has determined the priority. At that time, if the CPU is executing an instruction that disables interrupts, the CPU always executes the next instruction after the instruction execution is completed. 4.7.3 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, even if an interrupt request other than the NMI is issued during transfer, the interrupt is not accepted until the transfer is completed. If the NMI interrupt request is issued, NMI exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an NMI interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 4.7.4 IENR Clearing When an interrupt request is disabled by clearing the interrupt enable register or when the interrupt request register is cleared, the interrupt request should be masked (I bit = 1). If the above operation is executed while the I bit is 0 and contention between the instruction execution and the interrupt request generation occurs, exception handling, which corresponds to the interrupt request generated after instruction execution of the above operation is completed, is executed. Rev. 1.00 Dec. 18, 2006 Page 90 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators Section 5 Clock Pulse Generators Clock pulse generators provided on-chip include both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, system clock divider, and on-chip oscillator (available only for the mask ROM version). The subclock pulse generator consists of a subclock oscillator and subclock divider. Figure 5.1 (1) is a block diagram of the clock pulse generators for the flash memory version and figure 5.1 (2) shows those for the mask ROM version. OSC1 OSC2 System clock oscillator OSC (fOSC) System clock divider OSC OSC/8 OSC/16 OSC/32 OSC/64 /2 to /8192 System clock pulse generator W/2 X1 X2 Subclock oscillator W (fW) Subclock divider W/4 W/8 Prescaler S (13 bits) w w/4 SUB Subclock pulse generator w/2 Figure 5.1 Block Diagram of Clock Pulse Generators (Flash Memory Version) (1) Rev. 1.00 Dec. 18, 2006 Page 91 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators IRQAEC on-chip oscillator CLK OSC1 OSC2 System clock oscillator OSC OSC (fOSC) (fOSC) System clock divider OSC OSC/8 OSC/16 OSC/32 OSC/64 /2 to /8192 System clock pulse generator Prescaler S (13 bits) W W/2 X1 X2 Subclock oscillator fW (fW) Subclock divider W/4 W/8 W/4 SUB Subclock pulse generator W/2 Figure 5.1 Block Diagram of Clock Pulse Generators (Mask ROM Version) (2) The basic clock signals that drive the CPU and on-chip peripheral modules are and SUB. The system clock is divided by prescaler S to produce clock signals at rates from /8192 to /2. Both the system clock and subclock signals are provided to the on-chip peripheral modules. Since the on-chip oscillator is available for the mask ROM version, the reference clock can be selected as the output from the on-chip oscillator or system clock oscillator by the input level of the IRQAEC pin. Rev. 1.00 Dec. 18, 2006 Page 92 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators 5.1 Register Description * SUB32k control register (SUB32CR) * Oscillator Control Register (OSCCR) 5.1.1 SUB32k Control Register (SUB32CR) SUB32CR controls whether the subclock oscillator operates or stops. Bit 7 Bit Name 32KSTOP Initial Value 0 R/W R/W Description Subclock Oscillator Operation Control 0: Subclock oscillator operates 1: Subclock oscillator stops 6 5 to 0 0 All 0 R/W Reserved This bit is readable/writable. Reserved These bits cannot be modified. Rev. 1.00 Dec. 18, 2006 Page 93 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators 5.1.2 Oscillator Control Register (OSCCR) OSCCR contains flags indicating whether the system clock oscillator or on-chip oscillator is selected and the input level on the IRQAEC pin during resets; the former flag bit also controls whether the on-chip oscillator operates or not. Bit 7 to 3 2 Bit Name -- IRQAECF Initial Value All 0 -- R/W R/W R Description Reserved These bits are readable/writable enable reserves bits. IRQAEC flag This bit indicates the IRQAEC pin input level set during resets. 0: IRQAEC pin set to GND during resets 1: IRQAEC pin set to Vcc during resets 1 OSCF -- R OSC flag This bit indicates the oscillator operating with the system clock pulse generator. 0: System clock oscillator operating (on-chip oscillator stopped) 1: On-chip oscillator operating (system clock oscillator stopped) 0 -- 0 R/W Reserved Never write 1 to this bit, as it can cause the LSI to malfunction. Rev. 1.00 Dec. 18, 2006 Page 94 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators 5.2 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. 5.2.1 Connecting a Crystal Resonator Figure 5.2 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance crystal resonator should be used. For details, refer to section 23, Electrical Characteristics. C1 OSC 1 OSC 2 R1 C2 R1 = 1 M 20% Note: Consult with the crystal resonator manufacturer to determine the circuit constants. C1 , C2 Product Type Recommendation Value 12 pF 20% Frequency 4.19 MHz Manufacturer KYOCERA HC-49/U-S KINSEKI CORP. Figure 5.2 Typical Connection to Crystal Resonator 5.2.2 Connecting a Ceramic Resonator Figure 5.3 shows a typical method of connecting a ceramic resonator. C1 OSC1 Rf Rf = 1 M 20% Note: Consult with the crystal resonator manufacturer to determine the circuit constants. C2 OSC2 Frequency Manufacturer Product Type C1, C2 Recommendation Value 4.194 MHz Murata Manufacturing CSTLS4M19G53-B0 15pF (on-chip) CSTLS4M19G56-B0 47pF (on-chip) Co., Ltd. Figure 5.3 Typical Connection to Ceramic Resonator Rev. 1.00 Dec. 18, 2006 Page 95 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators 5.2.3 External Clock Input Method Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 5.4 shows a typical connection. The duty cycle of the external clock signal must be from 45 to 55%. OSC1 External clock input OSC2 Open Figure 5.4 Example of External Clock Input 5.2.4 On-Chip Oscillator Selection Method (Supported only by the Mask ROM Version) The on-chip oscillator is selected by the input level of the IRQAEC pin during a reset. The selection method of the system clock oscillator and the on-chip oscillator is listed in table 5.1. The input level of the IRQAEC pin during a reset* should be fixed either to Vcc or GND, depending on the oscillator type to be selected. When the on-chip oscillator is selected, to connect a resonator to OSC1 or OSC2 is not necessary. In this case, the OSC1 pin should be fixed to Vcc or GND. The setting becomes finally fixed and firm upon exit from a reset state. Note: * This reset represents an external reset or power-on reset, but not a reset by the watchdog timer. Table 5.1 Selection Method for System Clock Oscillator and On-Chip Oscillator 0 Enabled Disabled 1 Disabled Enabled IRQAEC Input Level (during a reset) System clock oscillator On-chip oscillator Rev. 1.00 Dec. 18, 2006 Page 96 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators 5.3 5.3.1 Subclock Generator Connecting 32.768-kHz/38.4-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz or 38.4-kHz crystal resonator, as shown in figure 5.5. Notes described in section 5.5.2, Notes on Board Design also apply to this connection. The 32KSTOP bit in the SUB32CR register can stop the subclock oscillator with the subclock oscillator program. To stop the subclock oscillator, set the SUB32CR register in active mode. When restoring from the subclock stopped condition, use the subclock after the oscillation stabilization time has elapsed, as the same as for the power supply. C1 X1 X2 C2 Frequency 38.4 kHz Note: Consult with the crystal resonator manufacturer to determine the circuit constants. Manufacturer Product Type C-4-Type C-001R Equivalent Series Resistance 30 k (max.) 35 k (max.) EPSON TOYOCOM Corp. 32.768 kHz EPSON TOYOCOM Corp. C1 = C 2 = 7pF Figure 5.5 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator 1. When using a resonator other than the above, ensure optimal conditions by conducting sufficient evaluation of consistency in cooperation with the manufacturer of the resonator. Even if the above resonators or products equivalent to them are implemented, their oscillation characteristics are affected by the board design. Be sure to use the actual board to evaluate consistency as a system. 2. The consistency as a system has to be verified not only in a reset state (i.e., the RES is driven low) but also in a state where a reset state has been exited (i.e., the low-level RES signal has been driven high). Figure 5.6 shows the equivalent circuit of the crystal resonator. Rev. 1.00 Dec. 18, 2006 Page 97 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators CS LS X1 RS X2 CO C O = 0.9 pF (typ.) R S = 14 k (typ.) f W = 32.768 kHz/38.4 kHz Figure 5.6 Equivalent Circuit of 32.768-kHz/38.4-kHz Crystal Resonator 5.3.2 Pin Connection when not Using Subclock When the subclock is not used, connect the X1 pin to GND and leave the X2 pin open, as shown in figure 5.7. X1 GND X2 Open Figure 5.7 Pin Connection when not Using Subclock 5.3.3 How to Input External Clock Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 5.8. X1 External clock input X2 Open Figure 5.8 Pin Connection when Inputting External Clock Rev. 1.00 Dec. 18, 2006 Page 98 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators Frequency Duty Subclock (w) 45% to 55% 5.4 Prescalers This LSI is equipped with an on-chip prescaler (prescaler S). Prescaler S is a 13-bit counter using the system clock () as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. 5.4.1 Prescaler S Prescaler S is a 13-bit counter using the system clock () as its input clock. A divided output is used as an internal clock of an on-chip peripheral module. Prescaler S is initialized to H'0000 at a reset, and starts counting up on exit from the reset state. In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read from or write to prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. The division ratio can be set separately for each on-chip peripheral function. In active (medium-speed) mode and sleep mode, the output from prescaler S is a clock that has been input to prescaler S and then divided (: set by the MA1 and MA0 bits in SYSCR2). Rev. 1.00 Dec. 18, 2006 Page 99 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators 5.5 5.5.1 (1) Usage Notes Note on Resonators Resonator Characteristics and Board Design Effective resonator characteristics are strongly influenced by the board design and should be carefully evaluated by the users of both the mask ROM and flash memory versions, with reference to the examples given in this section. Since resonator circuit constants will differ with the resonator, the stray capacitance in the circuit on which it is mounted, and other factors, determine suitable constants in consultation with the resonator manufacturer. Design the circuit so that voltages exceeding maximum ratings are never applied across the oscillator pins. Figure 5.9 shows an example of crystal and ceramic resonator arrangement. (2) Prevention of Incorrect Operation When a microcontroller is operating, the internal power supply potential fluctuates somewhat in synchronization with the system clock. Depending on the characteristics of the individual resonator, the amplitude of oscillations immediately after the oscillation stabilization waiting time may be insufficiently large in that the oscillations are affected by the fluctuations in the power supply potential. In this state, the oscillation waveform may be disrupted, leading to an unstable system clock signal and incorrect operation of the microcomputer. If incorrect operation is encountered, change the setting of the standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to 4 in the system control register 1 (SYSCR1)) to provide a longer wait. For example, if operation is incorrect with a wait-time setting of 1,024 cycles, check operation with a setting of 2,048 cycles or more. If the same kind of incorrect operation occurs in the transition from the reset state, hold the RES pin low for a longer period. Rev. 1.00 Dec. 18, 2006 Page 100 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators P37 X1 X2 Vss OSC2 OSC1 TEST (Vss) Figure 5.9 Example of Crystal and Ceramic Resonator Arrangement Rev. 1.00 Dec. 18, 2006 Page 101 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators Figure 5.10 (1) shows an example measuring circuit with the negative resistance recommended by the resonator manufacturer. Note that if the negative resistance of the circuit is less than that recommended by the resonator manufacturer, it may be difficult to start the main oscillator. If it is determined that oscillation does not occur because the negative resistance is lower than the level recommended by the resonator manufacturer, the circuit must be modified as shown in figure 5.10 (2) through (4). Which of the modification suggestions to use and the capacitor capacitance should be decided based upon evaluation results such as the negative resistance and the frequency deviation. Modification point OSC1 C1 Rf OSC2 C2 Negative resistance, addition of -R (1) Negative Resistance Measuring Circuit (2) Oscillator Circuit Modification Suggestion 1 C2 C1 Rf OSC2 OSC1 Modification point Modification point OSC1 C1 Rf C1 C3 OSC1 Rf OSC2 OSC2 C2 C2 (3) Oscillator Circuit Modification Suggestion 2 (4) Oscillator Circuit Modification Suggestion 3 Figure 5.10 Negative Resistance Measurement and Circuit Modification Suggestions Rev. 1.00 Dec. 18, 2006 Page 102 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators 5.5.2 Notes on Board Design When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the resonator circuit to prevent induction from interfering with correct oscillation (see figure 5.11). Avoid Signal A Signal B C1 OSC1 C2 OSC2 Figure 5.11 Example of Incorrect Board Design Note: When a crystal resonator or ceramic resonator is connected, consult with the crystal resonator and ceramic resonator manufacturers to determine the circuit constants because the constants differ according to the resonator, stray capacitance of the mounting circuit, and so on. 5.5.3 Definition of Oscillation Stabilization Wait Time Figure 5.12 shows the oscillation waveform (OSC2), system clock (), and microcomputer operating mode when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an resonator connected to the system clock oscillator. As shown in figure 5.12, when a transition is made from a state where the system clock oscillator is halted to active (high-speed or medium-speed) mode, the sum of the following two times (oscillation stabilization time and wait time) is required. (1) Oscillation Start Time The time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until generation of the system clock is started. Rev. 1.00 Dec. 18, 2006 Page 103 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators (2) Wait Time The time required for the CPU and peripheral functions to begin operating after the oscillation waveform frequency and system clock have been generated. The wait time is selected by the STS2 to STS0 bits in SYSCR1. Oscillation waveform (OSC2) System clock () Oscillation start time Wait time Operating mode Standby mode, watch mode, or subactive mode Oscillation stabilization wait time Active (high-speed) mode or active (medium-speed) mode Interrupt accepted Figure 5.12 Oscillation Stabilization Wait Time The required oscillation stabilization time is identical with the oscillation stabilization time (trc) when power as specified by the AC characteristics is supplied. The setting must be such that the time specified by the STS2 to STS0 bits in SYSCR is not less than trc. Consequently, when a resonator is connected as the system clock oscillator and a transition is made from the standby, watch, or subactive mode to the active (high- or medium-speed) mode, be sure to sufficiently test behavior on the actual circuit. Waiting time must be enough for the amplitudes of OSC1 and OSC2 to get sufficiently large. Since the oscillation start time varies with the constant of the actual circuit and stray capacitance, determine the oscillation stabilization waiting time in close cooperation with the manufacturer of the resonator. Rev. 1.00 Dec. 18, 2006 Page 104 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators 5.5.4 Note on Subclock Stop State In stopping the subclock, a state transition should only be made to a mode in which the system clock operates. A transition to any other mode may lead to incorrect operation. 5.5.5 Note on Using Power-On Reset The power-on reset circuit of this LSI allows adjustment of the reset cancellation time through the capacitance of the capacitor that is externally connected to the RES pin. Adjust the capacitance to ensure that the time required for oscillation to stabilize elapses before exit from the reset state. For details, see section 20, Power-On Reset Circuit. Rev. 1.00 Dec. 18, 2006 Page 105 of 568 REJ09B0348-0100 Section 5 Clock Pulse Generators Rev. 1.00 Dec. 18, 2006 Page 106 of 568 REJ09B0348-0100 Section 6 Power-Down Modes Section 6 Power-Down Modes This LSI has eight modes of operation after a reset. These include a normal active (high-speed) mode and seven power-down modes, in which power consumption is significantly reduced. The module standby function reduces power consumption by selectively halting on-chip module functions. * Active (medium-speed) mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from osc/8, osc/16, osc/32, and osc/64. * Subactive mode The CPU and all on-chip peripheral modules are operable on the subclock. The subclock frequency can be selected from w/2, w/4, and w/8. * Sleep (high-speed) mode The CPU halts. On-chip peripheral modules are operable on the system clock. * Sleep (medium-speed) mode The CPU halts. On-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from osc/8, osc/16, osc/32, and osc/64. * Subsleep mode The CPU halts. The on-chip peripheral modules are operable on the subclock. The subclock frequency can be selected from w/2, w/4, and w/8. * Watch mode The CPU halts. The on-chip peripheral modules are operable on the subclock. * Standby mode The CPU and all on-chip peripheral modules halt. * Module standby function Independent of the above modes, power consumption can be reduced by halting on-chip peripheral modules that are not used in module units. Note: In this manual, active (high-speed) mode and active (medium-speed) mode are collectively called active mode. Rev. 1.00 Dec. 18, 2006 Page 107 of 568 REJ09B0348-0100 Section 6 Power-Down Modes 6.1 Register Descriptions The registers related to power-down modes are as follows. * System control register 1 (SYSCR1) * System control register 2 (SYSCR2) * Clock halt registers 1 and 2 (CKSTPR1 and CKSTPR2) 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby Selects the mode to transit after the execution of the SLEEP instruction. 0: A transition is made to sleep mode or subsleep mode. 1: A transition is made to standby mode or watch mode. For details, see table 6.2. 6 5 4 STS2 STS1 STS0 0 0 0 R/W R/W R/W Standby Timer Select 2 to 0 Designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, subsleep mode, or watch mode to active mode or sleep mode due to an interrupt. The designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation stabilization time. The relationship between the specified value and the number of wait states is shown in table 6.1. When an external clock is to be used, the minimum value (STS2 = 1, STS1 = 0, STS0 = 1) is recommended. When the on-chip oscillator is to be used, the recommended values are STS2 = 0, STS1 = 1, and STS0 = 0. If the setting other than the recommended value is made, operation may start before the end of the waiting time. Rev. 1.00 Dec. 18, 2006 Page 108 of 568 REJ09B0348-0100 Section 6 Power-Down Modes Bit 3 Bit Name LSON Initial Value 0 R/W R/W Description Selects the system clock () or subclock (SUB) as the CPU operating clock when watch mode is cleared. 0: The CPU operates on the system clock () 1: The CPU operates on the subclock (SUB) 2 TMA3 0 R/W Selects the mode to which the transition is made after the SLEEP instruction is executed with bits SSBY and LSON in SYSCR1 and bits DTON and MSON in SYSCR2. For details, see table 6.2. Active Mode Clock Select 1 and 0 Select the operating clock in active (medium-speed) mode and sleep (medium-speed) mode. The MA1 and MA0 bits should be written to in active (high-speed) mode or subactive mode. 00: OSC/8 01: OSC/16 10: OSC/32 11: OSC/64 1 0 MA1 MA0 1 1 R/W R/W Table 6.1 Operating Frequency and Waiting Time Bit Operating Frequency STS0 Waiting Time 2 MHz 4.19 MHz 10 MHz STS2 STS1 0 0 0 1 8,192 states 16,384 states 1,024 states 2,048 states 4,096 states 2 states (external clock input) 4.1 8.2 0.512 1.024 2.048 0.001 1.953 3.907 0.244 0.488 0.977 0.0005 0.819 1.638 0.1024 0.2048 0.4096 0.0002 1 0 1 1 0 0 1 1 0 1 8 states 16 states 0.004 0.008 0.0019 0.0038 0.0008 0.0016 Note: Time unit is ms. When an external clock is input, bits STS2 to STS0 should be set as external clock input mode before mode transition is executed. When an external clock is not used, these bits should not be set as external clock input mode. Rev. 1.00 Dec. 18, 2006 Page 109 of 568 REJ09B0348-0100 Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Bit 7 to 5 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 4 NESEL 1 R/W Noise Elimination Sampling Frequency Select The subclock pulse generator generates the watch clock signal (W) and the system clock pulse generator generates the oscillator clock (OSC). This bit selects the sampling frequency of OSC when W is sampled. When OSC = 2 to 10 MHz, clear this bit to 0. When on-chip oscillator is to be used, set this bit to 1. 0: Sampling rate is OSC/16. 1: Sampling rate is OSC/4. 3 DTON 0 R/W Direct Transfer on Flag Selects the mode to which the transition is made after the SLEEP instruction is executed with bits SSBY, TMA3, and LSON in SYSCR1 and bit MSON in SYSCR2. For details, see table 6.2. 2 MSON 0 R/W Medium Speed on Flag After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. 0: Operation in active (high-speed) mode 1: Operation in active (medium-speed) mode 1 0 SA1 SA0 0 0 R/W R/W Subactive Mode Clock Select 1 and 0 Select the operating clock frequency in subactive and subsleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed. 00: W/8 01: W/4 1X: W/2 [Legend] X: Don't care. Rev. 1.00 Dec. 18, 2006 Page 110 of 568 REJ09B0348-0100 Section 6 Power-Down Modes 6.1.3 Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2) CKSTPR1 and CKSTPR2 allow the on-chip peripheral modules to enter the standby state in module units. * CKSTPR1 Bit 7 6 Bit Name S4CKSTP* 1 Initial Value 1 1 R/W R/W* R/W 1 Description SCI4 Module Standby SCI4 enters standby mode when this bit is cleared to 0. SCI3 Module Standby*2 SCI31 enters standby mode when this bit is cleared to 0. S31CKSTP 5 S32CKSTP 1 R/W SCI3 Module Standby*2 SCI32 enters standby mode when this bit is cleared to 1 0.* 4 ADCKSTP 1 R/W A/D Converter Module Standby A/D converter enters standby mode when this bit is cleared to 0. 3 -- 1 -- Reserved These bits are always read as 1 and cannot be modified. 2 TFCKSTP 1 R/W Timer F Module Standby Timer F enters standby mode when this bit is cleared to 0. 1 FROMCKSTP* 4 1 R/W Flash Memory Module Standby Flash memory enters standby mode when this bit is cleared to 0. 0 RTCCKSTP 1 R/W RTC Module Standby RTC enters standby mode when this bit is cleared to 0. Rev. 1.00 Dec. 18, 2006 Page 111 of 568 REJ09B0348-0100 Section 6 Power-Down Modes * CKSTPR2 Bit 7 Bit Name Initial Value R/W R/W Description Address Break Module Standby The address break enters standby mode when this bit is cleared to 0. 6 TPUCKSTP 1 R/W TPU Module Standby The TPU enters standby mode when this bit is cleared to 0. 5 IICCKSTP 1 R/W IIC2 Module Standby The IIC2 enters standby mode when this bit is cleared to 0. 4 PW2CKSTP ADBCKSTP 1 1 R/W PWM2 Module Standby The PWM2 enters standby mode when this bit is cleared to 0. 3 AECCKSTP 1 R/W Asynchronous Event Counter Module Standby The asynchronous event counter enters standby mode when this bit is cleared to 0. 2 WDCKSTP 1 R/W*3 Watchdog Timer Module Standby The watchdog timer enters standby mode when this bit is cleared to 0. 1 PW1CKSTP 1 R/W PWM1 Module Standby The PWM1 enters standby mode when this bit is cleared to 0. 0 -- 1 R Reserved Only 1 can be written to this bit. Notes: 1. This is a reserved bit which is not readable/writable in the masked ROM version. 2. When the SCI module standby is set, all registers in the SCI3 enter the reset state. 3. This bit is valid when the WDON bit in TCSRW is 0. If this bit is cleared to 0 while the WDON bit is set to 1 (while the watchdog timer is operating), this bit is cleared to 0. However, the watchdog timer does not enter module standby mode and continues operating. When the watchdog timer stops operating and the WDON bit is cleared to 0 by software, this bit is valid and the watchdog timer enters module standby mode. 4. This bit should be set to 1 when the E7 is used. Rev. 1.00 Dec. 18, 2006 Page 112 of 568 REJ09B0348-0100 Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state of the program. A direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program. RES input enables transitions from a mode to the reset state. Table 6.2 shows the transition conditions of each mode after the SLEEP instruction is executed and a mode to return by an interrupt. Table 6.3 shows the internal states of the LSI in each mode. Rev. 1.00 Dec. 18, 2006 Page 113 of 568 REJ09B0348-0100 Section 6 Power-Down Modes Reset state Program halt state Standby mode SLEEP d instruction 4 d SLEEP instruction Program execution state Active (high-speed mode) g f SLEEP instruction 4 SLEEP instruction SLEEP instruction a 3 a Pn EE ctio SL tru s in Pn EE tio SL truc s in Program halt state Sleep (high-speed) mode b SLEEP b instruction e SLEEP instruction 1 e S ins LE tru EP cti on Active (medium-speed) mode j SLEEP instruction i h SLEEP instruction SLEEP instruction i SLEEP instruction 3 Sleep (medium-speed) mode 1 Watch mode e SLEEP instruction 1 Subactive mode SLEEP instruction c Subsleep 2 mode Power-down modes Mode Transition Conditions (2) : Transition is made after exception handling is executed. Mode Transition Conditions (1) LSON a b c d e f g h i j 0 0 1 0 * 0 0 0 1 0 MSON SSBY 0 1 * * * 0 1 1 * 0 0 0 0 1 1 0 0 1 1 1 TMA3 * * 1 0 1 * * 1 1 1 DTON 0 0 0 0 0 1 1 1 1 1 * Don't care 3 4 2 1 Interrupt Sources RTC, timer F, IRQ0 interrupt, AEC, WKP7 to WKP0 interrupts RTC, timer F, TPU, SCI3 interrupt, IRQ4, IRQ3, IRQ1, IRQ0, IRQAEC interrupts, WKP7 to WKP0 interrupts, AEC All interrupts IRQ1, IRQ0, WKP7 to WKP0 interrupts, AEC Note: A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure that interrupt handling is accepted. Figure 6.1 Mode Transition Diagram Rev. 1.00 Dec. 18, 2006 Page 114 of 568 REJ09B0348-0100 Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling Transition Mode after SLEEP State Transition Before Instruction Mode due to Transition LSON MSON SSBY TMA3 DTON Execution Interrupt Active (highspeed) mode 0 0 0 * 0 Sleep (highspeed) mode Sleep (mediumspeed) mode Standby mode Standby mode Watch mode Watch mode Watch mode Active (highspeed) mode (direct transition) Active (mediumspeed) mode (direct transition) Subactive mode (direct transition) Active (highspeed) mode Symbol in Figure 6.1 a 0 1 0 * 0 Active (mediumspeed) mode Active (highspeed) mode Active (mediumspeed) mode Active (highspeed) mode Active (mediumspeed) mode b 0 0 0 1 1 1 0 0 0 0 d d 0 0 0 1 1 1 1 1 0 0 e e 1 0 * 0 1 0 1 * 0 1 Subactive mode e 0 1 0 * 1 g 1 * 1 1 1 i Rev. 1.00 Dec. 18, 2006 Page 115 of 568 REJ09B0348-0100 Section 6 Power-Down Modes Transition Mode after SLEEP Transition State Before Instruction Mode due to Transition LSON MSON SSBY TMA3 DTON Execution Interrupt Active (mediumspeed) mode 0 0 0 * 0 Sleep (highspeed) mode Sleep (mediumspeed) mode Standby mode Standby mode Watch mode Watch mode Watch mode Active (highspeed) mode (direct transition) Active (mediumspeed) mode (direct transition) Subactive mode (direct transition) Active (highspeed) mode Symbol in Figure 6.1 a 0 1 0 * 0 Active (mediumspeed) mode Active (highspeed) mode Active (mediumspeed) mode Active (highspeed) mode Active (mediumspeed) mode b 0 0 0 1 1 1 0 0 0 0 d d 0 0 0 1 1 1 1 1 0 0 e e 1 0 1 0 1 0 1 * 0 1 Subactive mode e 0 1 0 * 1 g 1 * 1 1 1 i Rev. 1.00 Dec. 18, 2006 Page 116 of 568 REJ09B0348-0100 Section 6 Power-Down Modes Transition Mode after SLEEP State Transition Before Instruction Mode due to Transition LSON MSON SSBY TMA3 DTON Execution Interrupt Subactive mode 1 0 0 * 0 1 0 1 1 1 1 1 0 0 0 Subsleep mode Watch mode Watch mode Watch mode Active (highspeed) mode (direct transition) Active (mediumspeed) mode (direct transition) Subactive mode (direct transition) Symbol in Figure 6.1 Subactive mode c Active (highspeed) mode Active (mediumspeed) mode e e 1 0 * 0 1 1 1 1 0 1 Subactive mode e j 0 1 1 1 1 h 1 * 1 1 1 [Legend] *: Don't care. Rev. 1.00 Dec. 18, 2006 Page 117 of 568 REJ09B0348-0100 Section 6 Power-Down Modes Table 6.3 Internal State in Each Operating Mode Active Mode MediumHigh-speed speed Functioning Functioning Functioning Functioning Functioning Functioning Sleep Mode Mediumspeed Functioning Functioning Halted Retained Subactive Watch Mode Mode Halted Functioning Halted Retained Halted Functioning Functioning Subsleep Mode Halted Functioning Halted Retained Stand-by Mode Halted Functioning Halted Retained Function System clock oscillator Subclock oscillator CPU Instructions RAM Registers I/O External interrupts IRQ0 IRQ1 IRQ3 IRQ4 IRQAEC WKP7 to WKP0 Peripheral modules RTC Asynchronous event counter Timer F TPU WDT SCI3/IrDA IIC2 PWM A/D converter High-speed Functioning Functioning Halted Retained Retained*1 Functioning Functioning Functioning Functioning Functioning Retained*5 Retained* 5 Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning/ 10 reta-ined* Functioning Functioning/ Functioning/r Functioning/ reta-ined*10 eta-ined*10 reta-ined*10 Functioning Functioning*6 Functioning*6 Functioning Functioning/ reta-ined*7 Retained Functioning* / retained 9 Functioning/ Functioning/r Retained reta-ined*7 eta-ined*7 Re-tained 9 Re-tained 9 Retained 9 Functioning* / Functioning* / Functioning* / retained retained retained Reset Retained Retained Retained Functioning/ Functioning/r Reset reta-ined*2 eta-ined*2 Retained Retained Retained Retained Retained Retained Retained Retained Retained Notes: 1. Register contents are retained. Output is the high-impedance state. 2. Functioning if W/2 is selected as an internal clock, or halted and retained otherwise. 3. Functioning if w, w/2, or w/4 is selected as a clock to be used. Halted and retained otherwise. 4. Functioning if the timekeeping time-base function is selected. 5. An external interrupt request is ignored. Contents of the interrupt request register are not affected. 6. The counter can be incremented. 7. Functioning if w/4 is selected as an internal clock. Halted and retained otherwise. 8. Functioning if w/32 is selected as an internal clock. Halted and retained otherwise. 9. Functioning if the on-chip oscillator is selected. 10. Functioning if the internal time keeping time-base function is selected and retained if the interval timer is selected. Rev. 1.00 Dec. 18, 2006 Page 118 of 568 REJ09B0348-0100 Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the system clock oscillator, subclock oscillator, and on-chip peripheral modules function. In sleep (medium-speed) mode, the on-chip peripheral modules function at the clock frequency set by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained. Sleep mode is cleared by an interrupt. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable bit. After sleep mode is cleared, a transition is made from sleep (high-speed) mode to active (high-speed) mode or from sleep (medium-speed) mode to active (medium-speed) mode. When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. Since an interrupt request signal is synchronous with the system clock, the maximum time of 2/ (s) may be delayed from the point at which an interrupt request signal occurs until the interrupt exception handling is started. Furthermore, it sometimes operates with half state early timing at the time of transition to sleep (medium-speed) mode. 6.2.2 Standby Mode In standby mode, the system clock oscillator stops, so the CPU and on-chip peripheral modules stop functioning when the WDT disables the on-chip oscillator operation. However, as long as the rated voltage is supplied, the contents of CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O ports go to the high-impedance state. Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, standby mode is cleared and interrupt exception handling starts. After standby mode is cleared, a transition is made to active (high-speed) or active (medium-speed) mode according to the MSON bit in SYSCR2. Standby mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable bit. When the RES pin goes low, the system clock oscillator starts. Since system clock signals are supplied to the entire chip as soon as the system clock oscillator starts functioning, the RES pin must be kept low until the system clock oscillator output stabilizes (except when the power-on Rev. 1.00 Dec. 18, 2006 Page 119 of 568 REJ09B0348-0100 Section 6 Power-Down Modes reset circuit is used). After the oscillator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high (except when the power-on reset circuit is used). 6.2.3 Watch Mode In watch mode, the system clock oscillator (when the WDT disables the on-chip oscillator operation) and CPU operation stop and on-chip peripheral modules stop functioning except for the RTC, timer F, and asynchronous event counter. However, as long as the rated voltage is supplied, the contents of CPU registers, some on-chip peripheral module registers, and on-chip RAM are retained. The I/O ports retain their state before the transition. Watch mode is cleared by an interrupt. When an interrupt is requested, watch mode is cleared and interrupt exception handling starts. When watch mode is cleared by an interrupt, a transition is made to active (high-speed) mode, active (medium-speed) mode, or subactive mode depending on the settings of the LSON bit in SYSCR1 and the MSON bit in SYSCR2. When the transition is made to active mode, after the time set in bits STS2 to STS0 in SYSCR1 has elapsed, interrupt exception handling starts. Watch mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable register. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high. 6.2.4 Subsleep Mode In subsleep mode, the CPU operation stops but on-chip peripheral modules other than the A/D converter and PWM function. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition. Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. After subsleep mode is cleared, a transition is made to subactive mode. Subsleep mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable register. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high. Rev. 1.00 Dec. 18, 2006 Page 120 of 568 REJ09B0348-0100 Section 6 Power-Down Modes 6.2.5 Subactive Mode In subactive mode, the system clock oscillator stops but on-chip peripheral modules other than the A/D converter, and PWM function. As long as a required voltage is applied, the contents of some registers of the on-chip peripheral modules are retained. Subactive mode is cleared by the SLEEP instruction. When subacitve mode is cleared, a transition to subsleep mode, active mode, or watch mode is made, depending on the combination of bits SSBY, LSON, and TMA3 in SYSCR1 and bits MSON and DTON in SYSCR2. Subactive mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable register. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized, the CPU starts reset exception handling if the RES pin is driven high. The operating frequency of subactive mode is selected from W/2, W/4, and W/8 by the SA1 and SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to the frequency which is set before the execution. 6.2.6 Active (Medium-Speed) Mode In active (medium-speed) mode, the system clock oscillator, subclock oscillator, CPU, and onchip peripheral module function. Active (medium-speed) mode is cleared by the SLEEP instruction. When active (medium-speed) mode is cleared, a transition to standby mode is made depending on the combination of bits SSBY, LSON, and TMA3 in SYSCR1, a transition to watch mode is made depending on the combination of bits SSBY and TMA3 in SYSCR1, or a transition to sleep mode is made depending on the combination of bits SSBY and LSON in SYSCR1. Moreover, a transition to active (high-speed) mode or subactive mode is made by a direct transition. Active (medium-sleep) mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register. When the RES pin goes low, the CPU goes into the reset state and active (medium-sleep) mode is cleared. Furthermore, it sometimes operates with half state early timing at the time of transition to active (medium-speed) mode. In active (medium-speed) mode, the on-chip peripheral modules function at the clock frequency set by the MA1 and MA0 bits in SYSCR1. Rev. 1.00 Dec. 18, 2006 Page 121 of 568 REJ09B0348-0100 Section 6 Power-Down Modes 6.3 Direct Transition The CPU can execute programs in two modes: active and subactive mode. A direct transition is a transition between these two modes without stopping program execution. A direct transition can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct transition also enables operating frequency modification in active or subactive mode. After the mode transition, direct transition interrupt exception handling starts. If the direct transition interrupt is disabled by IENR2, a transition is made instead to sleep or watch mode. Note: If a direct transition is attempted while the I bit in CCR is set to 1, sleep or watch mode will be entered, and the resulting mode cannot be exited. (1) Direct transfer from active (high-speed) mode to active (medium-speed) mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0 and the MSON and DTON bits in SYSCR2 are set to 1, a transition is made to active (medium-speed) mode via sleep mode. For the time required for transition, see section 6.3.1, Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode. (2) Direct transfer from active (medium-speed) mode to active (high-speed) mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. For the time required for transition, see section 6.3.2, Direct Transition from Active (High-Speed) Mode to Subactive Mode. (3) Direct transfer from active (high-speed) mode to subactive mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY, TMA3, and LSON bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is made to subactive mode via watch mode. For the time required for transition, see section 6.3.3, Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode. (4) Direct transfer from subactive mode to active (high-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made directly to active (highRev. 1.00 Dec. 18, 2006 Page 122 of 568 REJ09B0348-0100 Section 6 Power-Down Modes speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed. For the time required for transition, see section 6.3.4, Direct Transition from Active (Medium-Speed) Mode to Subactive Mode. (5) Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY, TMA3, and LSON bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is made to subactive mode via watch mode. For the time required for transition, see section 6.3.5, Direct Transition from Subactive Mode to Active (High-Speed) Mode. (6) Direct transfer from subactive mode to active (medium-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, and the MSON and DTON bits in SYSCR2 are set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed. For the time required for transition, see section 6.3.6, Direct Transition from Subactive Mode to Active (Medium-Speed) Mode. 6.3.1 Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tcyc before transition) + (Number of interrupt exception handling execution states) x (tcyc after transition) .....................(1) Example: When OSC/8 is selected as the operating clock before transition: Direct transition time = (2 + 1) x 1tosc + 14 x 8tosc = 115tosc [Legend] tosc: OSC clock cycle time tcyc: System clock () cycle time Rev. 1.00 Dec. 18, 2006 Page 123 of 568 REJ09B0348-0100 Section 6 Power-Down Modes 6.3.2 Direct Transition from Active (High-Speed) Mode to Subactive Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tcyc before transition) + (Number of interrupt exception handling execution states) x (tsubcyc after transition) .....................(2) Example: When osc/8 is selected as the operating clock before transition: Direct transition time = (2 + 1) x 1tosc + 14 x 1tsubcyc = 3tosc + 14tsubcyc [Legend] tosc: OSC clock cycle time tsubcyc: Subclock (SUB) cycle time 6.3.3 Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (3). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tcyc before transition) + (Number of interrupt exception handling execution states) x (tcyc after transition) ....................(3) Example: When OSC/8 is selected as the operating clock before transition: Direct transition time = (2 + 1) x 8tosc + 14 x 1tosc = 38tosc [Legend] tosc: OSC clock cycle time tcyc: System clock () cycle time Rev. 1.00 Dec. 18, 2006 Page 124 of 568 REJ09B0348-0100 Section 6 Power-Down Modes 6.3.4 Direct Transition from Active (Medium-Speed) Mode to Subactive Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (4). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tcyc before transition) + (Number of interrupt exception handling execution states) x (tsubcyc after transition) .....................(4) Example: When osc/8 is selected as the operating clock before transition: Direct transition time = (2 + 1) x 8tosc + 14 x 1tsubcyc = 24tosc + 14tsubcyc [Legend] tosc: OSC clock cycle time tsubcyc: Subclock (SUB) cycle time 6.3.5 Direct Transition from Subactive Mode to Active (High-Speed) Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (5). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tsubcyc before transition) + {(Wait time set in bits STS2 to STS0) + (Number of interrupt exception handling execution states)} x (tcyc after transition) ....................(5) Example: When w/8 is selected as the operating clock before transition and wait time = 8192 states: Direct transition time = (2 + 1) x 8tw + (8192 + 14) x 1tosc = 24tw + 8206tosc [Legend] tosc: OSC clock cycle time tw: Watch clock cycle time tcyc: System clock () cycle time tsubcyc: Subclock (SUB) cycle time Rev. 1.00 Dec. 18, 2006 Page 125 of 568 REJ09B0348-0100 Section 6 Power-Down Modes 6.3.6 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (6). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tsubcyc before transition) + {(Wait time set in bits STS2 to STS0) + (Number of interrupt exception handling execution states)} x (tcyc after transition) ....................(6) Example: When w/8 or OSC/8 is selected as the operating clock before transition and wait time = 8192 states) Direct transition time = (2 + 1) x 8tw + (8192 + 14) x 8tosc = 24tw + 65648tosc [Legend] tosc: OSC clock cycle time tw: Watch clock cycle time tcyc: System clock () cycle time tsubcyc: Subclock (SUB) cycle time 6.3.7 (1) Notes on External Input Signal Changes before/after Direct Transition Direct transition from active (high-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 6.5.2, Notes on External Input Signal Changes before/after Standby Mode. (2) Direct transition from active (medium-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 6.5.2, Notes on External Input Signal Changes before/after Standby Mode. (3) Direct transition from subactive mode to active (high-speed) mode Since the mode transition is performed via watch mode, see section 6.5.2, Notes on External Input Signal Changes before/after Standby Mode. Rev. 1.00 Dec. 18, 2006 Page 126 of 568 REJ09B0348-0100 Section 6 Power-Down Modes (4) Direct transition from subactive mode to active (medium-speed) mode Since the mode transition is performed via watch mode, see section 6.5.2, Notes on External Input Signal Changes before/after Standby Mode. 6.4 Module Standby Function The module-standby function can be set to any peripheral module. In module standby mode, the clock supply to modules stops to enter the power-down mode. Module standby mode enables each on-chip peripheral module to enter the standby state by clearing a bit that corresponds to each module in CKSTPR1 and CKSTPR2 to 0 and cancels the mode by setting the bit to 1. (See section 6.1.3, Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2).) 6.5 6.5.1 Usage Notes Standby Mode Transition and Pin States When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed) mode while the SSBY and TMA3 bits in SYSCR1 are set to 1 and the LSON bit in SYSCR1 is cleared to 0, a transition is made to standby mode. At the same time, pins go to the highimpedance state (except pins for which the pull-up MOS is designated as on). Figure 6.2 shows the timing in this case. Internal data bus SLEEP instruction fetch Next instruction fetch Internal processing High-impedance Standby mode SLEEP instruction execution Pins Port output Active (high-speed) mode or active (medium-speed) mode Figure 6.2 Standby Mode Transition and Pin States Rev. 1.00 Dec. 18, 2006 Page 127 of 568 REJ09B0348-0100 Section 6 Power-Down Modes 6.5.2 (1) Notes on External Input Signal Changes before/after Standby Mode When External Input Signal Changes before/after Standby Mode or Watch Mode When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and lowlevel widths of the signal must be at least two cycles of system clock or subclock SUB (referred to together in this section as the internal clock). As the internal clock stops in standby mode and watch mode, the width of external input signals requires careful attention when a transition is made via these operating modes. Ensure that external input signals conform to the conditions stated in (3), Recommended Timing of External Input Signals, below. (2) When External Input Signals cannot be Captured because Internal Clock Stops The case of falling edge capture is shown in figure 6.3. As shown in the case marked "Capture not possible," when an external input signal falls immediately after a transition to active mode or subactive mode, after oscillation is started by an interrupt via a different signal, the external input signal cannot be captured if the high-level width at that point is less than 2 tcyc or 2 tsubcyc. (3) Recommended Timing of External Input Signals To ensure dependable capture of an external input signal, high- and low-level signal widths of at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch mode, as shown in "Capture possible: case 1." External input signal capture is also possible with the timing shown in "Capture possible: case 2" and "Capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured. Rev. 1.00 Dec. 18, 2006 Page 128 of 568 REJ09B0348-0100 Section 6 Power-Down Modes Active (high-speed, medium-speed) Operating mode mode or subactive mode Standby mode or watch mode Wait for oscActive (high-speed, medium-speed) illation mode or subactive mode stabilization tcyc tsubcyc or SUB External input signal tcyc tsubcyc tcyc tsubcyc tcyc tsubcyc Capture possible: case 1 Capture possible: case 2 Capture possible: case 3 Capture not possible Interrupt by different signal Figure 6.3 External Input Signal Capture when Signal Changes before/after Standby Mode or Watch Mode (4) Input Pins to which these Notes Apply IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, IRQAEC, TMIF, ADTRG, TIOCA1, TIOCB1, TIOCA2 and TIOCB2. Rev. 1.00 Dec. 18, 2006 Page 129 of 568 REJ09B0348-0100 Section 6 Power-Down Modes Rev. 1.00 Dec. 18, 2006 Page 130 of 568 REJ09B0348-0100 Section 7 ROM Section 7 ROM The features of the 52-kbyte flash memory built into the flash memory (F-ZTAT) version are summarized below. * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 1 kbyte x 4 blocks, 28 kbytes x 1 block, 16 kbytes x 1 block, and 4 kbytes x 1 block. To erase the entire flash memory, each block must be erased in turn. * On-board programming On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Programmer mode Flash memory can be programmed/erased in programmer mode using a PROM programmer, as well as in on-board programming mode. * Automatic bit rate adjustment For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets software protection against flash memory programming/erasing. * Power-down mode Operation of the power supply circuit can be partly halted in subactive mode. As a result, flash memory can be read with low power consumption. * Module standby mode Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 6.4, Module Standby Function.) When the on-chip debugger is used, the bit 1 (FROMCKSTP) in clock stop register 1 (CKSTPR1) should be set to 1. Rev. 1.00 Dec. 18, 2006 Page 131 of 568 REJ09B0348-0100 Section 7 ROM 7.1 Block Configuration Figure 7.1 shows the block configuration of flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The 52-kbyte flash memory is divided into 1 kbyte x 4 blocks, 28 kbytes x 1 block, 16 kbytes x 1 block, and 4 kbytes x 1 block. Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80. Rev. 1.00 Dec. 18, 2006 Page 132 of 568 REJ09B0348-0100 Section 7 ROM H'0000 Erase unit 1 kbyte H'0001 H'0081 H'0002 H'0082 Programming unit: 128 bytes H'007F H'00FF H'0080 H'0380 H'0400 Erase unit 1 kbyte H'0381 H'0401 H'0481 H'0382 H'0402 H'0482 Programming unit: 128 bytes H'03FF H'047F H'04FF H'0480 H'0780 H'0800 Erase unit 1 kbyte H'0781 H'0801 H'0881 H'0782 H'0802 H'0882 Programming unit: 128 bytes H'07FF H'087F H'08FF H'0880 H'0B80 H'0C00 Erase unit 1 kbyte H'0B81 H'0C01 H'0C81 H'0B82 H'0C02 H'0C82 Programming unit: 128 bytes H'0BFF H'0C7F H'0CFF H'0C80 H'0F80 H'1000 Erase unit 28 kbytes H'0F81 H'1001 H'1081 H'0F82 H'1002 H'1082 Programming unit: 128 bytes H'0FFF H'107F H'10FF H'1080 H'7F80 H'8000 Erase unit 16 kbytes H'7F81 H'8001 H'8081 H'7F82 H'8002 H'8082 Programming unit: 128 bytes H'7FFF H'807F H'80FF H'8080 H'BF80 H'C000 Erase unit 4 kbytes H'BF81 H'C001 H'C081 H'CF81 H'BF82 H'C002 H'C082 H'CF82 H'BFFF H'C07F H'C0FF H'CFFF H'C080 H'CF80 Figure 7.1 Flash Memory Block Configuration Rev. 1.00 Dec. 18, 2006 Page 133 of 568 REJ09B0348-0100 Section 7 ROM 7.2 Register Descriptions The flash memory has the following registers. * * * * * Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory power control register (FLPWCR) Flash memory enable register (FENR) Flash Memory Control Register 1 (FLMCR1) 7.2.1 FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash Memory Programming/Erasing. Bit 7 6 Bit Name SWE Initial Value 0 0 R/W R/W Description Reserved This bit is always read as 0. Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, other FLMCR1 register bits and all EBR1 bits cannot be set. 5 ESU 0 R/W Erase Setup When this bit is set to 1, the flash memory changes to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. Set this bit to 1 before setting the E bit to 1 in FLMCR1. 4 PSU 0 R/W Program Setup When this bit is set to 1, the flash memory changes to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P bit in FLMCR1. 3 EV 0 R/W Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. Rev. 1.00 Dec. 18, 2006 Page 134 of 568 REJ09B0348-0100 Section 7 ROM Bit 2 Bit Name PV Initial Value 0 R/W R/W Description Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1 while SWE=1 and ESU=1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1 while SWE=1 and PSU=1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled. 7.2.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. Bit 7 Bit Name FLER Initial Value 0 R/W R Description Flash Memory Error Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. See section 7.5.3, Error Protection, for details. 6 to 0 All 0 Reserved These bits are always read as 0. Rev. 1.00 Dec. 18, 2006 Page 135 of 568 REJ09B0348-0100 Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0. Bit 7 6 5 4 3 2 1 0 Bit Name EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved This bit is always read as 0. When this bit is set to 1, 4 kbytes of H'C000 to H'CFFF will be erased. When this bit is set to 1, 16 kbytes of H'8000 to H'BFFF will be erased. When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF will be erased. When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF will be erased. When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF will be erased. When this bit is set to 1, 1 kbyte of H'0400 to H'07FF will be erased. When this bit is set to 1, 1 kbyte of H'0000 to H'03FF will be erased. Rev. 1.00 Dec. 18, 2006 Page 136 of 568 REJ09B0348-0100 Section 7 ROM 7.2.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read. Bit 7 Bit Name PDWND Initial Value 0 R/W R/W Description Power-Down Disable When this bit is 0 and a transition is made to subactive mode, the flash memory enters the power-down mode. When this bit is 1, the flash memory remains in the normal mode even after a transition is made to subactive mode. 6 to 0 All 0 Reserved These bits are always read as 0. 7.2.5 Flash Memory Enable Register (FENR) Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR1, and FLPWCR. Bit 7 Bit Name FLSHE Initial Value 0 R/W R/W Description Flash Memory Control Register Enable Flash memory control registers can be accessed when this bit is set to 1. Flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 All 0 Reserved These bits are always read as 0. Rev. 1.00 Dec. 18, 2006 Page 137 of 568 REJ09B0348-0100 Section 7 ROM 7.3 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1. The input level of each pin must be defined four states before the reset ends. When changing to boot mode, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI3 (channel 1). After erasing the entire flash memory, the programming control program is executed. This can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. In user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. Table 7.1 TEST 0 0 1 [Legend] Setting Programming Modes NMI 1 0 X P36 X 1 X PB0 X X 0 PB1 X X 0 PB2 X X 0 LSI State after Reset End User Mode Boot Mode Programmer Mode X: Don't care. Rev. 1.00 Dec. 18, 2006 Page 138 of 568 REJ09B0348-0100 Section 7 ROM 7.3.1 Boot Mode Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing. 2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. The inversion function of TXD and RXD pins by SPCR is set to "Not to be inverted," so do not put the circuit for inverting a value between the host and this LSI. 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host. The reset should end with the RXD pin high. The RXD and TXD pins should be pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 7.3. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F780 to H'FEEF is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. Before branching to the programming control program, the chip terminates transfer operations by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of program data or verify data with the host. The TXD pin is high (PCR42 = 1, P42 = 1). The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, as the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at least 20 states, and then setting the NMI pin. Boot mode is also cleared when a WDT overflow occurs. Rev. 1.00 Dec. 18, 2006 Page 139 of 568 REJ09B0348-0100 Section 7 ROM 8. Do not change the TEST pin and NMI pin input levels in boot mode. Boot Mode Operation Host Operation Processing Contents Communication Contents LSI Operation Processing Contents Branches to boot program at reset-start. Table 7.2 Item Boot mode initiation Boot program initiation Bit rate adjustment Continuously transmits data H'00 at specified bit rate. H'00, H'00 . . . H'00 Transmits data H'55 when data H'00 is received error-free. H'00 * Measures low-level period of receive data H'00. * Calculates bit rate and sets BRR in SCI3. * Transmits data H'00 to host as adjustment end indication. H'55 reception. H'55 Flash memory erase Boot program erase error H'FF H'AA reception H'AA Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.) Transfer of number of bytes of programming control program Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) Upper bytes, lower bytes Echoback Echobacks the 2-byte data received to host. Transmits 1-byte of programming control program (repeated for N times) H'XX Echoback Echobacks received data to host and also transfers it to RAM. (repeated for N times) H'AA reception H'AA Transmits data H'AA to host. Branches to programming control program transferred to on-chip RAM and starts execution. Rev. 1.00 Dec. 18, 2006 Page 140 of 568 REJ09B0348-0100 Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible System Clock Frequency Range of LSI 8 to 10 MHz 4 to 10 MHz 2 to 10 MHz Host Bit Rate 9,600 bps 4,800 bps 2,400 bps 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. As the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot mode. Figure 7.2 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing. Rev. 1.00 Dec. 18, 2006 Page 141 of 568 REJ09B0348-0100 Section 7 ROM Reset-start No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program Branch to user program/erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode Rev. 1.00 Dec. 18, 2006 Page 142 of 568 REJ09B0348-0100 Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 7.4.1, Program/Program-Verify and section 7.4.2, Erase/Erase-Verify, respectively. 7.4.1 Program/Program-Verify When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 7.3 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation according to table 7.4, and additional programming data computation according to table 7.5. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Table 7.6 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately 6.6 ms is allowed. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits are B'00. Verify data can be read in words or in longwords from the address to which a dummy write was performed. Rev. 1.00 Dec. 18, 2006 Page 143 of 568 REJ09B0348-0100 Section 7 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. Write pulse application subroutine Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 s Set P bit in FLMCR1 Wait (Wait time=programming time) Clear P bit in FLMCR1 Wait 5 s Clear PSU bit in FLMCR1 Wait 5 s Disable WDT START Set SWE bit in FLMCR1 Wait 1 s * Store 128-byte program data in program data area and reprogram data area n= 1 m= 0 Write 128-byte data in RAM reprogram data area consecutively to flash memory Apply Write pulse Set PV bit in FLMCR1 Wait 4 s Set block start address as verify address nn+1 H'FF dummy write to verify address End Sub Wait 2 s Read verify data Increment address Verify data = write data? * No m=1 No Yes n6? Yes Additional-programming data computation Reprogram data computation No 128-byte data verification completed? Yes Clear PV bit in FLMCR1 Wait 2 s n 6? Yes Successively write 128-byte data from additionalprogramming data area in RAM to flash memory Sub-Routine-Call Apply Write Pulse No Yes No m= 0 ? Yes Clear SWE bit in FLMCR1 Wait 100 s End of programming n 1000 ? No Clear SWE bit in FLMCR1 Wait 100 s Programming failure Note: *The RTS instruction must not be used during the following 1. and 2. periods. 1. A period between 128-byte data programming to flash memory and the P bit clearing 2. A period between dummy writing of H'FF to a verify address and verify data reading Figure 7.3 Program/Program-Verify Flowchart Rev. 1.00 Dec. 18, 2006 Page 144 of 568 REJ09B0348-0100 Section 7 ROM Table 7.4 Reprogram Data Computation Table Verify Data 0 1 0 1 Reprogram Data 1 0 1 1 Comments Programming completed Reprogram bit Remains in erased state Program Data 0 0 1 1 Table 7.5 Additional-Program Data Computation Table Verify Data 0 1 0 1 Additional-Program Data 0 1 1 1 Comments Additional-program bit No additional programming No additional programming No additional programming Reprogram Data 0 0 1 1 Table 7.6 Programming Time Programming Time 30 200 In Additional Programming 10 Comments n (Number of Writes) 1 to 6 7 to 1,000 Note: Time shown in s. Rev. 1.00 Dec. 18, 2006 Page 145 of 568 REJ09B0348-0100 Section 7 ROM 7.4.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An overflow cycle of approximately 19.8 ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. Interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out. Rev. 1.00 Dec. 18, 2006 Page 146 of 568 REJ09B0348-0100 Section 7 ROM Erase start SWE bit 1 Wait 1 s n1 Set EBR1 Enable WDT ESU bit 1 Wait 100 s E bit 1 Wait 10 ms E bit 0 Wait 10 s ESU bit 10 10 s Disable WDT EV bit 1 Wait 20 s Set block start address as verify address H'FF dummy write to verify address Wait 2 s Read verify data No Increment address Verify data + all 1s ? Yes No Last address of block ? Yes EV bit 0 Wait 4 s EV bit 0 Wait 4s * nn+1 No All erase block erased ? Yes SWE bit 0 Wait 100 s End of erasing n 100 ? No SWE bit 0 Wait 100 s Erase failure Yes Note: * The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading. Figure 7.4 Erase/Erase-Verify Flowchart Rev. 1.00 Dec. 18, 2006 Page 147 of 568 REJ09B0348-0100 Section 7 ROM 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 7.5.2 Software Protection Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to H'00, erase protection is set for all blocks. 7.5.3 Error Protection In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling excluding a reset during programming/erasing * When a SLEEP instruction is executed during programming/erasing Rev. 1.00 Dec. 18, 2006 Page 148 of 568 REJ09B0348-0100 Section 7 ROM The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P or E bit. However, PV and EV bit settings are retained, and a transition can be made to verify mode. Error protection can be cleared only by a reset. 7.6 Programmer Mode In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU device type with the on-chip 64-kbyte flash memory (FZTAT64V5). 7.7 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the following states: * Normal operating mode The flash memory can be read and written to at high speed. * Power-down operating mode The power supply circuit of flash memory can be partly halted. As a result, flash memory can be read with low power consumption. * Standby mode All flash memory circuits are halted. Table 7.7 shows the correspondence between the operating modes of this LSI and the flash memory. In subactive mode, the flash memory can be set to operate in power-down mode with the PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from power-down mode or standby mode, a period to stabilize operation of the power supply circuits that were stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to STS0 in SYSCR1 must be set to provide a wait time of at least 20 s, even when the external clock is being used. Rev. 1.00 Dec. 18, 2006 Page 149 of 568 REJ09B0348-0100 Section 7 ROM Table 7.7 Flash Memory Operating States Flash Memory Operating State LSI Operating State Active mode Subactive mode Sleep mode Subsleep mode Standby mode PDWND = 0 (Initial Value) Normal operating mode Power-down mode Normal operating mode Standby mode Standby mode PDWND = 1 Normal operating mode Normal operating mode Normal operating mode Standby mode Standby mode 7.8 Notes on Setting Module Standby Mode When the flash memory is set to enter module standby mode, the system clock supply is stopped to the module, the function is stopped, and the state is the same as that in standby mode. Also program operation is stopped in the flash memory. Therefore operation program should be transferred to the RAM and the program should run in the RAM. Then the flash memory should be set to enter module standby mode. When an interrupt is generated in module standby mode, the vector address cannot be read and the program malfunctions. Before the flash memory is set to enter module standby mode, the corresponding bit in the interrupt enable register should be cleared to 0 and the I bit in CCR should be set to 1. Then after the flash memory enters module standby mode, NMI and address break interrupt requests should not be generated. Figure 7.5 shows a module standby mode setting. Rev. 1.00 Dec. 18, 2006 Page 150 of 568 REJ09B0348-0100 Section 7 ROM Transfer execution program to RAM (user area) Clear corresponding bit in interrupt enable register to 0 Set I bit in CCR to 1 Jump to address of execution program in RAM Clear FROMCKSTP bit in CRSTPR1 to 0 Figure 7.5 Module Standby Mode Setting Rev. 1.00 Dec. 18, 2006 Page 151 of 568 REJ09B0348-0100 Section 7 ROM Rev. 1.00 Dec. 18, 2006 Page 152 of 568 REJ09B0348-0100 Section 8 RAM Section 8 RAM Microcontrollers of the H8/38776 group have an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Product Classification Flash memory version Mask ROM version H8/38776F H8/38776 H8/38775 H8/38774 H8/38773 RAM Size 3 kbytes 2 kbytes 2 kbytes 1 kbyte 1 kbyte RAM Address H'F380 to H'FF7F H'F780 to H'FF7F H'F780 to H'FF7F H'FB80 to H'FF7F H'FB80 to H'FF7F Rev. 1.00 Dec. 18, 2006 Page 153 of 568 REJ09B0348-0100 Section 8 RAM Rev. 1.00 Dec. 18, 2006 Page 154 of 568 REJ09B0348-0100 Section 9 I/O Ports Section 9 I/O Ports Microcontrollers of the H8/38776 Group have 55 general I/O ports and eight general input-only ports. Port 9 is a large current port, which can drive 15 mA (@VOL = 1.0 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings. The registers for selecting these functions can be divided into two types: those included in I/O ports and those included in each onchip peripheral module. General I/O ports are comprised of the port control register for controlling inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit units. For details on the execution of bit manipulation instructions to the port data register (PDR), see section 2.8.3, Bit-Manipulation Instruction. For details on block diagrams for each port, see appendix B.1, I/O Port Block Diagrams. 9.1 Port 1 Port 1 is an I/O port also functioning as an SCI4 I/O pin, TPU I/O pin, and asynchronous event counter input pin. Figure 9.1 shows its pin configuration. P16/SCK4 P15/TIOCB2 Port 1 P14/TIOCA2/TCLKC P13/TIOCB1/TCLKB P12/TIOCA1/TCLKA P11/AEVL P10/AEVH Figure 9.1 Port 1 Pin Configuration Port 1 has the following registers. * * * * Port data register 1 (PDR1) Port control register 1 (PCR1) Port pull-up control register 1 (PUCR1) Port mode register 1 (PMR1) Rev. 1.00 Dec. 18, 2006 Page 155 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.1.1 Port Data Register 1 (PDR1) PDR1 is a register that stores data of port 1. Bit 7 6 5 4 3 2 1 0 Bit Name P16 P15 P14 P13 P12 P11 P10 Initial Value 1 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read. Bit 7 is reserved. This bit is always read as 1 and cannot be modified. 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit 7 6 5 4 3 2 1 0 Bit Name PCR16 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 Initial Value 1 0 0 0 0 0 0 0 R/W W W W W W W W Description Setting a PCR1 bit to 1 makes the corresponding pin (P16 to P10) an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid when the corresponding pin is designated as a general I/O pin. PCR1 is a write-only register. These bits are always read as 1. Bit 7 is reserved. This bit cannot be modified. Rev. 1.00 Dec. 18, 2006 Page 156 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.1.3 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS of the port 1 pins in bit units. Bit 7 6 5 4 3 2 1 0 Bit Name PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 Initial Value 1 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS. Bit 7 is reserved. This bit is always read as 1 and cannot be modified. 9.1.4 Port Mode Register 1 (PMR1) PMR1 controls the selection of functions for port 1 pins. Bit 7 to 2 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 1 AEVL 0 R/W P11/AEVL Pin Function Switch Selects whether pin P11/AEVL is used as P11 or as AEVL. 0: P11 I/O pin 1: AEVL input pin 0 AEVH 0 R/W P10/AEVH Pin Function Switch Selects whether pin P10/AEVH is used as P10 or as AEVH. 0: P10 I/O pin 1: AEVH input pin Rev. 1.00 Dec. 18, 2006 Page 157 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.1.5 Pin Functions The relationship between the register settings and the port functions is shown below. * P16/SCK4 pin The pin function is switched as shown below according to the combination of the CKS3 to CKS0 bits in SCSR4 and PCR16 bit in PCR1. CKS3* 1 1*1 Other than B'111*1 0 P16 input pin 1 P16 output pin B'111*1 x SCK4 input pin* 2 0*1 x*1 x SCK4 output pin*2 CKS2 to CKS0*1 PCR16 Pin Function [Legend] x: Don't care. TM Notes: 1. Supported only by the F-ZTAT version. 2. Only port function is available for the mask ROM version. Rev. 1.00 Dec. 18, 2006 Page 158 of 568 REJ09B0348-0100 Section 9 I/O Ports * P15/TIOCB2 pin The pin function is switched as shown below according to the combination of the TPU channel 2 setting by the MD1 and MD0 bits in TMDR_2, IOB3 to IOB0 bits in TIOR_2, and CCLR1 and CCLR0 bits in TCR_2, and the PCR15 bit in PCR1. TPU Channel 2 Setting PCR15 Pin Function Next table (1) 0 Next table (2) 1 0 Next table (3) 1 P15 input pin P15 output pin P15 input pin P15 output pin TIOCB2 input pin* TPU Channel 2 Setting MD1, MD0 IOB3 to IOB0 CCLR1, CCLR0 Output Function [Legend] x: Don't care. (2) (3) B'00 (1) B'10, B'01, B'11 B'0001 to B'0111 B'xx B'xxxx B'0000 B'1xxx Setting prohibited Rev. 1.00 Dec. 18, 2006 Page 159 of 568 REJ09B0348-0100 Section 9 I/O Ports * P14/TIOCA2/TCLKC pin The pin function is switched as shown below according to the combination of the TPU channel 2 setting by the MD1 and MD0 bits in TMDR_2, IOA3 to IOA0 bits in TIOR_2, and CCLR1 and CCLR0 bits in TCR_2, the TPSC2 to TPSC0 bits in TCR_2, and the PCR14 bit in PCR1. TPU Channel 2 Setting PCR14 Pin Function Next table (1) TIOCA2 output pin 0 P14 input pin 2 Next table (2) 1 P14 output pin 1 TIOCA2 input pin* TCLKC input pin* Notes: 1. When the MD1 and MD0 bits are set to B'00 and the IOA3 bit to 1, the pin function becomes the TIOCA2 input pin. 2. When the TPSC2 to TPSC0 bits in TCR_2 are set to B'110, the pin function becomes the TCLKC input pin. TPU Channel 2 Setting MD1, MD0 IOA3 to IOA0 B'0000 B'0100 B'1xxx (2) B'00 B'0001 to B'0011 B'0101 to B'0111 Output compare output (1) (2) B'1x B'xx00 Other than B'xx00 (1) (1) B'11 Other than B'xx00 (2) CCLR1, CCLR0 Output Function PWM mode 1* output Other than B'10 PWM mode 2 output B'10 [Legend] Note: * x: Don't care. The output of the TIOCB2 pin is disabled. Rev. 1.00 Dec. 18, 2006 Page 160 of 568 REJ09B0348-0100 Section 9 I/O Ports * P13/TIOCB1/TCLKB pin The pin function is switched as shown below according to the combination of the TPU channel 1 setting by the MD1 and MD0 bits in TMDR_1, IOB3 to IOB0 bits in TIOR_1, and CCLR1 and CCLR0 bits in TCR_1, the TPSC2 to TPSC0 bits in TCR_1 and TCR_2, and the PCR13 bit in PCR1. TPU Channel 1 Setting PCR13 Pin Function Next table (1) 0 Next table (2) 1 0 Next table (3) 1 P13 input pin P13 output pin P13 input pin P13 output pin TIOCB1 input pin TCLKB input pin* Note: * When the TPSC2 to TPSC0 bits in TCR_1 or TCR_2 are set to B'101, the pin function becomes the TCLKB input pin. (2) (3) B'00 B'0000 B'1xxx B'0001 to B'0111 B'xx Setting prohibited (1) B'10, B'01, B'11 B'xxxx TPU Channel 1 Setting MD1, MD0 IOB3 to IOB0 CCLR1, CCLR0 Output Function [Legend] x: Don't care. Rev. 1.00 Dec. 18, 2006 Page 161 of 568 REJ09B0348-0100 Section 9 I/O Ports * P12/TIOCA1/TCLKA pin The pin function is switched as shown below according to the combination of the TPU channel 1 setting by the MD1 and MD0 bits in TMDR_1, IOA3 to IOA0 bits in TIOR_1, and CCLR1 and CCLR0 bits in TCR_1, the TPSC2 to TPSC0 bits in TCR_1 and TCR_2, and the PCR12 bit in PCR1. TPU Channel 1 Setting PCR12 Pin Function Next table (1) TIOCA1 output pin 0 P12 input pin 2 Next table (2) 1 P12 output pin 1 TIOCA1 input pin* TCLKA input pin* Notes: 1. When the MD1 and MD0 bits are set to B'00 and the IOA3 bit to 1, the pin function becomes the TIOCA1 input pin. 2. When the TPSC2 to TPSC0 bits in TCR_1 or TCR_2 are set to B'100, the pin function becomes the TCLKA input pin. TPU Channel 1 Setting MD1, MD0 IOA3 to IOA0 B'0000 B'0100 B'1xxx (2) B'00 B'0001 to B'0011 B'0101 to B'0111 Output compare output (1) (2) B'1x B'xx00 (1) B'10 Other than B'xx00 (1) B'11 Other than B'xx00 (2) CCLR1, CCLR0 Output Function PWM mode 1* output Other than B'10 PWM mode 2 output B'10 [Legend] Note: * x: Don't care. The output of the TIOCB1 pin is disabled. Rev. 1.00 Dec. 18, 2006 Page 162 of 568 REJ09B0348-0100 Section 9 I/O Ports * P11/AEVL pin The pin function is switched as shown below according to the combination of the AEVL bit in PMR1 and PCR11 bit in PCR. AEVL PCR11 Pin Function [Legend] x: Don't care. 0 P11 input pin 0 1 P11 output pin 1 x AEVL input pin * P10/AEVH pin The pin function is switched as shown below according to the combination of the AEVH bit in PMR1 and PCR10 bit in PCR. AEVH PCR10 Pin Function [Legend] x: Don't care. 0 P10 input pin 0 1 P10 output pin 1 x AEVH input pin 9.1.6 Input Pull-Up MOS Port 1 has an on-chip input pull-up MOS function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset. (n = 6 to 0) PCR1n PUCR1n Input Pull-Up MOS [Legend] x: Don't care. 0 Off 0 1 On 1 x Off Rev. 1.00 Dec. 18, 2006 Page 163 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.2 Port 3 Port 3 is an I/O port also functioning as an SCI4 I/O pin, SCI3_2 I/O pin, IIC2 I/O pin, and RTC output pin. Figure 9.2 shows its pin configuration. P37/SO4 P36/SI4 Port 3 P32/TXD32/SCL P31/RXD32/SDA P30/SCK32/TMOW Figure 9.2 Port 3 Pin Configuration Port 3 has the following registers. * * * * Port data register 3 (PDR3) Port control register 3 (PCR3) Port pull-up control register 3 (PUCR3) Port mode register 3 (PMR3) Port Data Register 3 (PDR3) 9.2.1 PDR3 is a register that stores data of port 3. Bit 7 6 5 4 3 2 1 0 Bit Name P37 P36 P32 P31 P30 Initial Value 0 0 1 1 1 0 0 0 R/W R/W R/W R/W R/W R/W Description If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read. Bits 5 to 3 are reserved. These bits are always read as 1 and cannot be modified. Rev. 1.00 Dec. 18, 2006 Page 164 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.2.2 Port Control Register 3 (PCR3) PCR3 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 3. Bit 7 6 5 4 3 2 1 0 Bit Name PCR37 PCR36 PCR32 PCR31 PCR30 Initial Value 0 0 1 1 1 0 0 0 R/W W W W W W Description Setting a PCR3 bit to 1 makes the corresponding pin (P37, P36, P32 to P30) an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid when the corresponding pin is designated as a general I/O pin. PCR3 is a write-only register. These bits are always read as 1. Bits 5 to 3 are reserved. These bits cannot be modified. 9.2.3 Port Pull-Up Control Register 3 (PUCR3) PUCR3 controls the pull-up MOS of the port 3 pins in bit units. Bit 7 6 5 4 3 2 1 0 Bit Name PUCR37 PUCR36 PUCR30 Initial Value 0 0 1 1 1 1 1 0 R/W R/W R/W R/W Description When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS. Bits 5 to 1 are reserved. These bits are always read as 1 and cannot be modified. Rev. 1.00 Dec. 18, 2006 Page 165 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.2.4 Port Mode Register 3 (PMR3) PMR3 controls the selection of functions for port 3 pins. Bit 7 to 1 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 0 TMOW 0 R/W P30/SCK32/TMOW Pin Function Switch Selects whether pin P30/SCK32/TMOW is used as P30/SCK32 or as TMOW. 0: P30/SCK32 I/O pin 1: TMOW output pin 9.2.5 Pin Functions The relationship between the register settings and the port functions is shown below. * P37/SO4 pin The pin function is switched as shown below according to the combination of the TE bit in SCR4 and PCR37 bit in PCR3. TE* 1 0*1 0 P37 input pin 1 P37 output pin 1*1 x SO4 output pin*2 PCR37 Pin Function [Legend] x: Don't care. TM Notes: 1. Supported only by the F-ZTAT version. 2. Only port function is available for the masked ROM version. Rev. 1.00 Dec. 18, 2006 Page 166 of 568 REJ09B0348-0100 Section 9 I/O Ports * P36/SI4 pin The pin function is switched as shown below according to the combination of the RE bit in SCR4 and PCR36 bit in PCR3. RE* 1 0*1 0 P36 input pin 1 P36 output pin 1*1 x SI4 input pin*2 PCR36 Pin Function [Legend] x: Don't care. TM Notes: 1. Supported only by the F-ZTAT version. 2. Only port function is available for the masked ROM version. * P32/TXD32/SCL pin The pin function is switched as shown below according to the combination of the PCR32 bit in PCR3, ICE bit in ICRR1, TE32 bit in SCR32, and SPC32 bit in SPCR. ICE SPC32 TE32 PCR32 Pin Function [Legend] Note: * 0 P32 input pin 0 x 1 P32 output pin 0 1 x x 1 x x x TXD32 output pin* SCL output pin x: Don't care. When SPC32 = 1 and TE32 = 0, the TXD32 pin functionality is marking output. * P31/RXD32/SDA pin The pin function is switched as shown below according to the combination of the PCR31 bit in PCR3, ICE bit in ICCR1, and RE32 bit in SCR32. ICE RE32 PCR31 Pin Function [Legend] x: Don't care. 0 P31 input pin 0 1 P31 output pin 0 1 x RXD32 input pin 1 x x SDA I/O pin Rev. 1.00 Dec. 18, 2006 Page 167 of 568 REJ09B0348-0100 Section 9 I/O Ports * P30/SCK32/TMOW pin The pin function is switched as shown below according to the combination of the TMOW bit in PMR3, PCR30 bit in PCR3, CKE321 and CKE320 bits in SCR32, and COM32 bit in SMR32. TMOW CKE321 CKE320 COM32 PCR30 Pin Function [Legend] 0 P30 input pin 0 1 0 1 x 0 1 x 0 1 x x x 1 x x x x TMOW output pin P30 output SCK32 output pin SCK32 input pin pin x: Don't care. 9.2.6 Input Pull-Up MOS Port 3 has an on-chip input pull-up MOS function that can be controlled by software. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset. (n = 7, 6, 0) PCR3n PUCR3n Input Pull-Up MOS [Legend] x: Don't care. 0 Off 0 1 On 1 x Off Rev. 1.00 Dec. 18, 2006 Page 168 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.3 Port 4 Port 4 is an I/O port also functioning as an SCI3_1 data I/O pin and timer F I/O pin. Figure 9.3 shows its pin configuration. Port 4 P42/TXD31/IrTXD/TMOFH P41/RXD31/IrRXD/TMOFL P40/SCK31/TMIF Figure 9.3 Port 4 Pin Configuration Port 4 has the following registers. * Port data register 4 (PDR4) * Port control register 4 (PCR4) * Port mode register 4 (PMR4) 9.3.1 Port Data Register 4 (PDR4) PDR4 is a register that stores data of port 4. Bit 7 to 3 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 2 1 0 P42 P41 P40 0 0 0 R/W R/W R/W If port 4 is read while PCR4 bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is read while PCR4 bits are cleared to 0, the pin states are read. Rev. 1.00 Dec. 18, 2006 Page 169 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.3.2 Port Control Register 4 (PCR4) PCR4 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 4. Bit 7 to 3 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 2 1 0 PCR42 PCR41 PCR40 0 0 0 W W W Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR4 and in PDR4 are valid when the corresponding pin is designated as a general I/O pin. PCR4 is a write-only register. These bits are always read as 1. Rev. 1.00 Dec. 18, 2006 Page 170 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.3.3 Port Mode Register 4 (PMR4) PMR4 controls the selection of functions for port 4 pins. Bit 7 to 3 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 2 TMOFH 0 R/W P42/TXD31/IrTXD/TMOFH Pin Function Switch Selects whether pin P42/TXD31/IrTXD/TMOFH is used as P42 or TXD31/IrTXD, or as TMOFH. 0: P42 I/O pin or TXD31/IrTXD output pin 1: TMOFH output pin 1 TMOFL 0 R/W P41/RXD31/IrRXD/TMOFL Pin Function Switch Selects whether pin P41/RXD31/IrRXD/TMOFL is used as P41 or RXD31/IrRXD, or as TMOFL. 0: P41 I/O pin or RXD31/IrRXD input pin 1: TMOFL output pin 0 TMIF 0 R/W P40/SCK31/TMIF Pin Function Switch Selects whether pin P40/SCK31/TMIF is used as P40/SCK31 or as TMIF. 0: P40/SCK31 I/O pin 1: TMIF output pin Rev. 1.00 Dec. 18, 2006 Page 171 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.3.4 Pin Functions The relationship between the register settings and the port functions is shown below. * P42/TXD31/IrTXD/TMOFH pin The pin function is switched as shown below according to the combination of the TMOFH bit in PMR4, PCR42 bit in PCR4, IrE bit in IrCR, TE bit in SCR3, and SPC31 bit in SPCR. TMOFH SPC31 TE IrE PCR42 Pin Function [Legend] 0 P42 input pin 0 x x 1 P42 output pin 0 x TXD31 output pin 0 1 x 1 x IrTXD output pin 1 x x x x TMOFH output pin x: Don't care. * P41/RXD31/IrRXD/TMOFL pin The pin function is switched as shown below according to the combination of the TMOFL bit in PMR4, PCR41 bit in PCR4, IrE bit in IrCR, and RE bit in SCR3. TMOFL RE IrE PCR41 Pin Function [Legend] 0 P41 input pin 0 x 1 P41 output pin 0 x RXD31 input pin 0 1 1 x IrRXD input pin 1 x x x TMOFL output pin x: Don't care. Rev. 1.00 Dec. 18, 2006 Page 172 of 568 REJ09B0348-0100 Section 9 I/O Ports * P40/SCK31/TMIF pin The pin function is switched as shown below according to the combination of the TMIF bit in PMR4, PCR40 bit in PCR4, CKE1 and CKE0 bits in SCR3, and COM bit in SMR3. TMIF CKE1 CKE0 COM PCR40 Pin Function [Legend] 0 0 1 0 1 x 0 1 x 0 x x 0 1 1 x x 1 0 x x x P40 input P40 output SCK31 output pin pin pin SCK31 Setting TMIF input input pin prohibited pin x: Don't care. 9.4 Port 5 Port 5 is an I/O port also functioning as a wakeup interrupt input pin. Figure 9.4 shows its pin configuration. P57/WKP7 P56/WKP6 P55/WKP5 Port 5 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 Figure 9.4 Port 5 Pin Configuration Port 5 has the following registers. * * * * Port data register 5 (PDR5) Port control register 5 (PCR5) Port pull-up control register 5 (PUCR5) Port mode register 5 (PMR5) Rev. 1.00 Dec. 18, 2006 Page 173 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.4.1 Port Data Register 5 (PDR5) PDR5 is a register that stores data of port 5. Bit 7 6 5 4 3 2 1 0 Bit Name P57 P56 P55 P54 P53 P52 P51 P50 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read. 9.4.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Bit 7 6 5 4 3 2 1 0 Bit Name PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR5 and in PDR5 are valid when the corresponding pin is designated as a general I/O pin. PCR5 is a write-only register. These bits are always read as 1. Rev. 1.00 Dec. 18, 2006 Page 174 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.4.3 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS of the port 5 pins in bit units. Bit 7 6 5 4 3 2 1 0 Bit Name PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS. 9.4.4 Port Mode Register 5 (PMR5) PMR5 controls the selection of functions for port 5 pins. Bit 7 6 5 4 3 2 1 0 Bit Name WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P5n/WKPn Pin Function Switch These bits select whether the pin is used as P5n or WKPn. 0: P5n I/O pin 1: WKPn input pin (n = 7 to 0) Rev. 1.00 Dec. 18, 2006 Page 175 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.4.5 Pin Functions The relationship between the register settings and the port functions is shown below. * P57/WKP7 to P54/WKP4 pins The pin function is switched as shown below according to the combination of the WKPn bit in PMR5, PCR5n bit in PCR5. (n = 7 to 4) WKPn PCR5n Pin Function [Legend] x: Don't care. 0 P5n input pin 0 1 P5n output pin 1 x WKPn input pin * P53/WKP3 to P50/WKP0 pins The pin function is switched as shown below according to the combination of the WKPm bit in PMR5, PCR5m bit in PCR5. (m = 3 to 0) WKPm PCR5m Pin Function [Legend] x: Don't care. 0 P5m input pin 0 1 P5m output pin 1 x WKPm input pin Rev. 1.00 Dec. 18, 2006 Page 176 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.4.6 Input Pull-Up MOS Port 5 has an on-chip input pull-up MOS function that can be controlled by software. When the PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset. (n = 7 to 0) PCR5n PUCR5n Input Pull-Up MOS [Legend] x: Don't care. 0 Off 0 1 On 1 x Off 9.5 Port 6 Port 6 is an I/O port. Figure 9.5 shows its pin configuration. P67 P66 P65 Port 6 P64 P63 P62 P61 P60 Figure 9.5 Port 6 Pin Configuration Port 6 has the following registers. * Port data register 6 (PDR6) * Port control register 6 (PCR6) * Port pull-up control register 6 (PUCR6) Rev. 1.00 Dec. 18, 2006 Page 177 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.5.1 Port Data Register 6 (PDR6) PDR6 is a register that stores data of port 6. Bit 7 6 5 4 3 2 1 0 Bit Name P67 P66 P65 P64 P63 P62 P61 P60 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read. 9.5.2 Port Control Register 6 (PCR6) PCR6 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 6. Bit 7 6 5 4 3 2 1 0 Bit Name PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR6 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR6 and in PDR6 are valid when the corresponding pin is designated as a general I/O pin. PCR6 is a write-only register. These bits are always read as 1. Rev. 1.00 Dec. 18, 2006 Page 178 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.5.3 Port Pull-Up Control Register 6 (PUCR6) PUCR6 controls the pull-up MOS of the port 6 pins in bit units. Bit 7 6 5 4 3 2 1 0 Bit Name PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS. 9.5.4 Pin Functions The relationship between the register settings and the port functions is shown below. * P67 to P64 pins The pin function is switched as shown below according to the setting of the PCR6n bit in PCR6. (n = 7 to 4) PCR6n Pin Function 0 P6n input pin 1 P6n output pin Rev. 1.00 Dec. 18, 2006 Page 179 of 568 REJ09B0348-0100 Section 9 I/O Ports * P63 to P60 pins The pin function is switched as shown below according to the setting of the PCR6m bit in PCR6. (m = 3 to 0) PCR6m Pin Function 0 P6m input pin 1 P6m output pin 9.5.5 Input Pull-Up MOS Port 6 has an on-chip input pull-up MOS function that can be controlled by software. When the PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset. (n = 7 to 0) PCR6n PUCR6n Input Pull-Up MOS [Legend] x: Don't care. 0 Off 0 1 On 1 x Off Rev. 1.00 Dec. 18, 2006 Page 180 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.6 Port 7 Port 7 is an I/O port. Figure 9.6 shows its pin configuration. P77 P76 P75 Port 7 P74 P73 P72 P71 P70 Figure 9.6 Port 7 Pin Configuration Port 7 has the following registers. * Port data register 7 (PDR7) * Port control register 7 (PCR7) 9.6.1 Port Data Register 7 (PDR7) PDR7 is a register that stores data of port 7. Bit 7 6 5 4 3 2 1 0 Bit Name P77 P76 P75 P74 P73 P72 P71 P70 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read. Rev. 1.00 Dec. 18, 2006 Page 181 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.6.2 Port Control Register 7 (PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7. Bit 7 6 5 4 3 2 1 0 Bit Name PCR77 PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR7 and in PDR7 are valid when the corresponding pin is designated as a general I/O pin. PCR7 is a write-only register. These bits are always read as 1. 9.6.3 Pin Functions The relationship between the register settings and the port functions is shown below. * P77 to P74 pins The pin function is switched as shown below according to the setting of the PCR7n bit in PCR7. (n = 7 to 4) PCR7n Pin Function 0 P7n input pin 1 P7n output pin Rev. 1.00 Dec. 18, 2006 Page 182 of 568 REJ09B0348-0100 Section 9 I/O Ports * P73 to P70 pins The pin function is switched as shown below according to the setting of the PCR7m bit in PCR7. (m = 3 to 0) PCR7m Pin Function 0 P7m input pin 1 P7m output pin 9.7 Port 8 Port 8 is an I/O port. Figure 9.7 shows its pin configuration. P87 P86 P85 Port 8 P84 P83 P82 P81 P80 Figure 9.7 Port 8 Pin Configuration Port 8 has the following registers. * Port data register 8 (PDR8) * Port control register 8 (PCR8) Rev. 1.00 Dec. 18, 2006 Page 183 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.7.1 Port Data Register 8 (PDR8) PDR8 is a register that stores data of port 8. Bit 7 6 5 4 3 2 1 0 Bit Name P87 P86 P85 P84 P83 P82 P81 P80 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read. 9.7.2 Port Control Register 8 (PCR8) PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8. Bit 7 6 5 4 3 2 1 0 Bit Name PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR8 bit to 1 makes the corresponding pin (P87 to P80) an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR8 and in PDR8 are valid when the corresponding pin is designated as a general I/O pin. PCR8 is a write-only register. These bits are always read as 1. Rev. 1.00 Dec. 18, 2006 Page 184 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.7.3 Pin Functions The relationship between the register settings and the port functions is shown below. * P87 to P84 pins The pin function is switched as shown below according to the setting of the PCR8n bit in PCR8. (n = 7 to 4) PCR8n Pin Function 0 P8n input pin 1 P8n output pin * P83 to P80 pins The pin function is switched as shown below according to the setting of the PCR8m bit in PCR8. (m = 3 to 0) PCR8m Pin Function 0 P8m input pin 1 P8m output pin Rev. 1.00 Dec. 18, 2006 Page 185 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.8 Port 9 Port 9 is an I/O port also functioning as an external interrupt input pin and PWM output pin. Figure 9.8 shows its pin configuration. P93 Port 9 P92/IRQ4 P91/PWM2 P90/PWM1 Figure 9.8 Port 9 Pin Configuration Port 9 has the following registers. * Port data register 9 (PDR9) * Port control register 9 (PCR9) * Port mode register 9 (PMR9) 9.8.1 Port Data Register 9 (PDR9) PDR9 is a register that stores data of port 9. Bit 7 to 4 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 3 2 1 0 P93 P92 P91 P90 1 1 1 1 R/W R/W R/W R/W If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read. Rev. 1.00 Dec. 18, 2006 Page 186 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.8.2 Port Control Register 9 (PCR9) PCR9 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 9. Bit 7 to 4 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 3 2 1 0 PCR93 PCR92 PCR91 PCR90 0 0 0 0 W W W W Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR9 and in PDR9 are valid when the corresponding pin is designated as a general I/O pin. PCR9 is a write-only register. These bits are always read as 1. 9.8.3 Port Mode Register 9 (PMR9) PMR9 controls the selection of functions for port 9 pins. Bit 7 to 4 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 3 0 R/W Reserved Although this bit is readable/writable, 1 should not be written to this bit. 2 IRQ4 0 R/W P92/IRQ4 Pin Function Switch Selects whether pin P92/IRQ4 is used as P92 or as IRQ4. 0: P92 I/O pin 1: IRQ4 input pin Rev. 1.00 Dec. 18, 2006 Page 187 of 568 REJ09B0348-0100 Section 9 I/O Ports Bit 1 0 Bit Name PWM2 PWM1 Initial Value 0 0 R/W R/W R/W Description P9n/PWMn+1 Pin Function Switch Select whether pin P9n/PWMn+1 is used as P9n or as PWMn+1. (n = 1, 0) 0: P9n I/O pin 1: PWMn+1 output pin 9.8.4 Pin Functions The relationship between the register settings and the port functions is shown below. * P93 pin The pin function is switched as shown below according to the PCR93 bit in PCR9. PCR93 Pin Function 0 P93 input pin 1 P93 output pin * P92/IRQ4 pin The pin function is switched as shown below according to the combination of the IRQ4 bit in PMR9 and PCR92 bit in PCR9. IRQ4 PCR92 Pin Function 0 P92 input pin 0 1 P92 output pin 0 IRQ4 input pin 1 1 Setting prohibited * P91/PWM2, P90/PWM1 pins The pin function is switched as shown below according to the combination of the PWMn+1 bit in PMR9 and PCR9n bit in PCR9. (n = 1, 0) PWMn+1 PCR9n Pin Function [Legend] x: Don't care. 0 P9n input pin 0 1 P9n output pin 1 x PWMn+1 output pin Rev. 1.00 Dec. 18, 2006 Page 188 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.9 Port A Port A is an I/O port. Figure 9.9 shows its pin configuration. PA3 Port A PA2 PA1 PA0 Figure 9.9 Port A Pin Configuration Port A has the following registers. * Port data register A (PDRA) * Port control register A (PCRA) 9.9.1 Port Data Register A (PDRA) PDRA is a register that stores data of port A. Bit 7 to 4 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 3 2 1 0 PA3 PA2 PA1 PA0 0 0 0 0 R/W R/W R/W R/W If port A is read while PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If port A is read while PCRA bits are cleared to 0, the pin states are read. Rev. 1.00 Dec. 18, 2006 Page 189 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.9.2 Port Control Register A (PCRA) PCRA selects inputs/outputs in bit units for pins to be used as general I/O ports of port A. Bit 7 to 4 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 3 2 1 0 PCRA3 PCRA2 PCRA1 PCRA0 0 0 0 0 W W W W Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCRA and in PDRA are valid when the corresponding pin is designated as a general I/O pin. PCRA is a write-only register. These bits are always read as 1. Rev. 1.00 Dec. 18, 2006 Page 190 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.9.3 Pin Functions The relationship between the register settings and the port functions is shown below. * PA3 pin The pin function is switched as shown below according to the setting of the PCRA3 bit in PCRA. PCRA3 Pin Function 0 PA3 input pin 1 PA3 output pin * PA2 pin The pin function is switched as shown below according to the setting of the PCRA2 bit in PCRA. PCRA2 Pin Function 0 PA2 input pin 1 PA2 output pin * PA1 pin The pin function is switched as shown below according to the setting of the PCRA1 bit in PCRA. PCRA1 Pin Function 0 PA1 input pin 1 PA1 output pin * PA0 pin The pin function is switched as shown below according to the setting of the PCRA0 bit in PCRA. PCRA0 Pin Function 0 PA0 input pin 1 PA0 output pin Rev. 1.00 Dec. 18, 2006 Page 191 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.10 Port B Port B is an input-only port also functioning as an interrupt input pin and analog input pin. Figure 9.10 shows its pin configuration. PB7/AN7 PB6/AN6 PB5/AN5 Port B PB4/AN4 PB3/AN3 PB2/AN2/IRQ3 PB1/AN1/IRQ1 PB0/AN0/IRQ0 Figure 9.10 Port B Pin Configuration Port B has the following registers. * Port data register B (PDRB) * Port mode register B (PMRB) 9.10.1 Port Data Register B (PDRB) PDRB is a register that stores data of port B. Bit 7 6 5 4 3 2 1 0 Bit Name PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Initial Value R/W Description Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel by the CH3 to CH0 bits in AMR of the A/D converter or the AIN1, that pin is read as 0 regardless of the input voltage. Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R Rev. 1.00 Dec. 18, 2006 Page 192 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.10.2 Port Mode Register B (PMRB) PMRB controls the selection of the port B pin functions. Bit 7 to 5 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 4 ADTSTCHG 0 R/W TEST/ADTRG Pin Function Switch Selects whether pin TEST/ADTRG is used as TEST or as ADTRG. 0: TEST pin 1: ADTRG input pin For details on the setting of the ADTRG input pin, refer to section 18.4.2, External Trigger Input Timing. 3 2 IRQ3 1 0 R/W Reserved This bit is always read as 1 and cannot be modified. PB2/AN2/IRQ3 Pin Function Switch Selects whether pin PB2/AN2/IRQ3 is used as PB2/AN2 or as IRQ3. 0: PB2/AN2 input pin 1: IRQ3 input pin 1 IRQ1 0 R/W PB1/AN1/IRQ1 Pin Function Switch Selects whether pin PB1/AN1/IRQ1 is used as PB1/AN1 or as IRQ1. 0: PB1/AN1 input pin 1: IRQ1 input pin 0 IRQ0 0 R/W PB0/AN0/IRQ0 Pin Function Switch Selects whether pin PB0/AN0/IRQ0 is used as PB0/AN0 or as IRQ0. 0: PB0/AN0 input pin 1: IRQ0 input pin Rev. 1.00 Dec. 18, 2006 Page 193 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.10.3 Pin Functions The relationship between the register settings and the port functions is shown below. * PB7/AN7 pin The pin function is switched as shown below according to the CH3 to CH0 bits in AMR. CH3 to CH0 Pin Function Other than B'1011 PB7 input pin B'1011 AN7 input pin * PB6/AN6 pin The pin function is switched as shown below according to the CH3 to CH0 bits in AMR. CH3 to CH0 Pin Function Other than B'1010 PB6 input pin B'1010 AN6 input pin * PB5/AN5 pin The pin function is switched as shown below according to the CH3 to CH0 bits in AMR. CH3 to CH0 Pin Function Other than B'1001 PB5 input pin B'1001 AN5 input pin * PB4/AN4 pin The pin function is switched as shown below according to the CH3 to CH0 bits in AMR. CH3 to CH0 Pin Function Other than B'1000 PB4 input pin B'1000 AN4 input pin * PB3/AN3 pin The pin function is switched as shown below according to the CH3 to CH0 bits in AMR. CH3 to CH0 Pin Function Other than B'0111 PB3 input pin B'0111 AN3 input pin Rev. 1.00 Dec. 18, 2006 Page 194 of 568 REJ09B0348-0100 Section 9 I/O Ports * PB2/AN2/IRQ3 pin The pin function is switched as shown below according to the combination of the CH3 to CH0 bits in AMR and IRQ3 bit in PMRB. IRQ3 CH3 to CH0 Pin Function 0 Other than B'0110 PB2 input pin B'0110 AN2 input pin 1 Other than B'0110 IRQ3 input pin * PB1/AN1/IRQ1 pin The pin function is switched as shown below according to the combination of the CH3 to CH0 bits in AMR and IRQ1 bit in PMRB. IRQ1 CH3 to CH0 Pin Function Other than B'0101 PB1 input pin 0 B'0101 AN1 input pin 1 Other than B'0101 IRQ1 input pin * PB0/AN0/IRQ0 pin The pin function is switched as shown below according to the combination of the CH3 to CH0 bits in AMR and IRQ0 bit in PMRB. IRQ0 CH3 to CH0 Pin Function Other than B'0100 PB0 input pin 0 B'0100 AN0 input pin 1 Other than B'0100 IRQ0 input pin Rev. 1.00 Dec. 18, 2006 Page 195 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.11 9.11.1 Input/Output Data Inversion Serial Port Control Register (SPCR) SPCR switches input/output data inversion of the RXD (IrRXD) and TXD (IrTXD) pins. Figure 9.11 shows a input/output data inversion function. SCINV0 SCINV2 P31/RXD32 P41/RXD31/IrRXD RXD32 RXD31/IrRXD SCINV1 SCINV3 P32/TXD32 P42/TXD31/IrTXD TXD32 TXD31/IrTXD Figure 9.11 Input/Output Data Inversion Function Bit 7, 6 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 5 SPC32 0 R/W P32/TXD32/SCL Pin Function Switch Selects whether pin P32/TXD32/SCL is used as P32/SCL or as TXD32. 0: P32/SCL I/O pin 1: TXD32 output pin* Note: * Set the TE32 bit in SCR32 after setting this bit to 1. Rev. 1.00 Dec. 18, 2006 Page 196 of 568 REJ09B0348-0100 Section 9 I/O Ports Bit 4 Bit Name SPC31 Initial Value 0 R/W R/W Description P42/TXD31/IrTXD/TMOFH Pin Function Switch Selects whether pin P42/TXD31/IrTXD/TMOFH is used as P42/TMOFH or as TXD31/IrTXD. 0: P42 I/O pin or TMOFH output pin 1: TXD31/IrTXD output pin* Note: * Set the TE bit in SCR3 after setting this bit to 1. 3 SCINV3 0 R/W TXD32 Pin Output Data Inversion Switch Specifies whether the polarity of output data of the TXD32 pin is to be inverted or not. 0: Polarity of TXD32 output data is not inverted 1: Polarity of TXD32 output data is inverted 2 SCINV2 0 R/W RXD32 Pin Input Data Inversion Switch Specifies whether the polarity of input data of the RXD32 pin is to be inverted or not. 0: Polarity of RXD32 input data is not inverted 1: Polarity of RXD32 input data is inverted 1 SCINV1 0 R/W TXD31/IrTXD Pin Output Data Inversion Switch Specifies whether the polarity of output data of the TXD31/IrTXD pin is to be inverted or not. 0: Polarity of TXD31/IrTXD output data is not inverted 1: Polarity of TXD31/IrTXD output data is inverted 0 SCINV0 0 R/W RXD31/IrRXD Pin Input Data Inversion Switch Specifies whether the polarity of input data of the RXD31/IrRXD pin is to be inverted or not. 0: Polarity of RXD31/IrRXD input data is not inverted 1: Polarity of RXD31/IrRXD input data is inverted Note: When the serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying the serial port control register, modification must be made in a state in which data changes are invalidated. Rev. 1.00 Dec. 18, 2006 Page 197 of 568 REJ09B0348-0100 Section 9 I/O Ports 9.12 9.12.1 Usage Notes How to Handle Unused Pin If an I/O pin not used by the user system is floating, pull it up or down. * If an unused pin is an input pin, it is recommended to handle it in one of the following ways: Pull it up to Vcc with an on-chip pull-up MOS. Pull it up to Vcc with an external resistor of approximately 100 k. Pull it down to Vss with an external resistor of approximately 100 k. For a pin also used by the A/D converter, pull it up to AVcc. With an external resistor of approximately 100 k. * If an unused pin is an output pin, it is recommended to handle it in one of the following ways: Set the output of the unused pin to high and pull it up to Vcc with an external resistor of approximately 100 k. Set the output of the unused pin to low and pull it down to GND with an external resistor of approximately 100 k. Rev. 1.00 Dec. 18, 2006 Page 198 of 568 REJ09B0348-0100 Section 10 Realtime Clock (RTC) Section 10 Realtime Clock (RTC) The realtime clock (RTC) is a timer used to count time ranging from a second to a week. Interrupts can be generated ranging from 0.25 seconds to a week. Figure 10.1 shows the block diagram of the RTC. 10.1 * * * * * * * * Features Counts seconds, minutes, hours, and day-of-week Start/stop function Reset function Readable/writable counter of seconds, minutes, hours, and day-of-week with BCD codes Periodic (0.25 seconds, 0.5 seconds, one second, minute, hour, day, and week) interrupts 8-bit free running counter Selection of clock source Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 6.4, Module Standby Function.) PSS 32-kHz oscillator circuit RTCCSR 1/4 RSECDR RMINDR RHRDR TMOW Clock count control circuit RWKDR RTCCR1 RTCCR2 RTCFLG [Legend] RTCCSR: Clock source select register RSECDR: Second date register/ free running counter data register RMINDR: Minute date register RHRDR: Hour date register Interrupt control circuit RWKDR: RTCCR1: RTCCR2: RTCFLG: PSS: Day-of-week date register RTC control register 1 RTC control register 2 RTC interrupt flag register Prescaler S Figure 10.1 Block Diagram of RTC Rev. 1.00 Dec. 18, 2006 Page 199 of 568 REJ09B0348-0100 Internal data bus Interrupt Section 10 Realtime Clock (RTC) 10.2 Input/Output Pin Table 10.1 shows the RTC input/output pin. Table 10.1 Pin Configuration Name Clock output Abbreviation TMOW I/O Output Function RTC divided clock output 10.3 Register Descriptions The RTC has the following registers. * * * * * * * * Second data register/free running counter data register (RSECDR) Minute data register (RMINDR) Hour data register (RHRDR) Day-of-week data register (RWKDR) RTC control register 1 (RTCCR1) RTC control register 2 (RTCCR2) Clock source select register (RTCCSR) RTC Interrupt flag register (RTCFLG) Rev. 1.00 Dec. 18, 2006 Page 200 of 568 REJ09B0348-0100 Section 10 Realtime Clock (RTC) 10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR) RSECDR counts the BCD-coded second value. The setting range is decimal 00 to 59. It is an 8-bit read register used as a counter, when it operates as a free running counter. For more information on reading seconds, minutes, hours, and day-of-week, see section 10.4.3, Data Reading Procedure. Bit 7 Bit Name BSY Initial Value -- R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. Counting Ten's Position of Seconds Counts on 0 to 5 for 60-second counting. Counting One's Position of Seconds Counts on 0 to 9 once per second. When a carry is generated, 1 is added to the ten's position. 6 5 4 3 2 1 0 SC12 SC11 SC10 SC03 SC02 SC01 SC00 -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W 10.3.2 Minute Data Register (RMINDR) RMINDR counts the BCD-coded minute value on the carry generated once per minute by the RSECDR counting. The setting range is decimal 00 to 59. Bit 7 Bit Name BSY Initial Value -- R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. Counting Ten's Position of Minutes Counts on 0 to 5 for 60-minute counting. Counting One's Position of Minutes Counts on 0 to 9 once per minute. When a carry is generated, 1 is added to the ten's position. 6 5 4 3 2 1 0 MN12 MN11 MN10 MN03 MN02 MN01 MN00 -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W Rev. 1.00 Dec. 18, 2006 Page 201 of 568 REJ09B0348-0100 Section 10 Realtime Clock (RTC) 10.3.3 Hour Data Register (RHRDR) RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR. The setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in RTCCR1. Bit 7 Bit Name BSY Initial Value -- R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 3 2 1 0 -- HR11 HR10 HR03 HR02 HR01 HR00 0 -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W Reserved This bit is always read as 0. Counting Ten's Position of Hours Counts on 0 to 2 for ten's position of hours. Counting One's Position of Hours Counts on 0 to 9 once per hour. When a carry is generated, 1 is added to the ten's position. Rev. 1.00 Dec. 18, 2006 Page 202 of 568 REJ09B0348-0100 Section 10 Realtime Clock (RTC) 10.3.4 Day-of-Week Data Register (RWKDR) RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by RHRDR. The setting range is decimal 0 to 6 using bits WK2 to WK0. Bit 7 Bit Name BSY Initial Value -- R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 to 3 2 1 0 -- WK2 WK1 WK0 All 0 -- -- -- -- R/W R/W R/W Reserved These bits are always read as 0. Day-of-Week Counting Day-of-week is indicated with a binary code 000: Sunday 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Setting prohibited Rev. 1.00 Dec. 18, 2006 Page 203 of 568 REJ09B0348-0100 Section 10 Realtime Clock (RTC) 10.3.5 RTC Control Register 1 (RTCCR1) RTCCR1 controls start/stop and reset of the clock timer. For the definition of time expression, see figure 10.2. Bit 7 Bit Name RUN Initial Value -- R/W R/W Description RTC Operation Start 0: Stops RTC operation 1: Starts RTC operation 6 12/24 -- R/W Operating Mode 0: RTC operates in 12-hour mode. RHRDR counts on 0 to 11. 1: RTC operates in 24-hour mode. RHRDR counts on 0 to 23. 5 PM -- R/W A.m./P.m. 0: Indicates a.m. when RTC is in the 12-hour mode. 1: Indicates p.m. when RTC is in the 12-hour mode. 4 RST 0 R/W Reset 0: Normal operation 1: Resets registers and control circuits except RTCCSR and this bit. Clear this bit to 0 after having been set to 1. 3 -- 0 -- Reserved This bit is always read as 0. Only 0 should be written to this bit. 2 to 0 -- All 0 -- Reserved These bits are always read as 0. Noon 24-hour count 0 12-hour count 0 PM 1 1 2 2 3 3 4 4 567 567 0 (Morning) 8 8 9 10 11 12 13 14 15 16 17 9 10 11 0 1 2 3 4 5 1 (Afternoon) 24-hour count 18 19 20 21 22 23 0 12-hour count 6 7 8 9 10 11 0 1 (Afternoon) 0 PM Figure 10.2 Definition of Time Expression Rev. 1.00 Dec. 18, 2006 Page 204 of 568 REJ09B0348-0100 Section 10 Realtime Clock (RTC) 10.3.6 RTC Control Register 2 (RTCCR2) RTCCR2 controls RTC periodic interrupts of week, day, hour, minute, one second, 0.5 seconds, and 0.25 seconds. Enabling interrupts of week, day, hour, minute, one second, 0.5 seconds, and 0.25 seconds sets the corresponding flag to 1 in the RTC interrupt flag register (RTCFLG) when an interrupt occurs. It also controls an overflow interrupt of a free running counter when RTC operates as a free running counter. Bit 7 Bit Name FOIE Initial Value -- R/W R/W Description Free Running Counter Overflow Interrupt Enable 0: Disables an overflow interrupt 1: Enables an overflow interrupt 6 WKIE -- R/W Week Periodic Interrupt Enable 0: Disables a week periodic interrupt 1: Enables a week periodic interrupt 5 DYIE -- R/W Day Periodic Interrupt Enable 0: Disables a day periodic interrupt 1: Enables a day periodic interrupt 4 HRIE -- R/W Hour Periodic Interrupt Enable 0: Disables an hour periodic interrupt 1: Enables an hour periodic interrupt 3 MNIE -- R/W Minute Periodic Interrupt Enable 0: Disables a minute periodic interrupt 1: Enables a minute periodic interrupt 2 1SEIE -- R/W One-Second Periodic Interrupt Enable 0: Disables a one-second periodic interrupt 1: Enables a one-second periodic interrupt 1 05SEIE -- R/W 0.5-Second Periodic Interrupt Enable 0: Disables a 0.5-second periodic interrupt 1: Enables a 0.5-second periodic interrupt 0 025SEIE -- R/W 0.25-Second Periodic Interrupt Enable 0: Disables a 0.25-second periodic interrupt 1: Enables a 0.25-second periodic interrupt Rev. 1.00 Dec. 18, 2006 Page 205 of 568 REJ09B0348-0100 Section 10 Realtime Clock (RTC) 10.3.7 Clock Source Select Register (RTCCSR) RTCCSR selects clock source. A free running counter controls start/stop of counter operation by the RUN bit in RTCCR1. When a clock other than w/4 is selected, the RTC is disabled and operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running counter, RSECDR enables counter values to be read. An interrupt can be generated by setting 1 to the FOIE bit in RTCCR2 and enabling an overflow interrupt of the free running counter. A clock in which the system clock is divided by 32, 16, 8, or 4 is output in active or sleep mode. Bit 7 6 5 4 Bit Name -- RCS6 RCS5 SUB32K Initial Value 0 0 0 0 R/W -- R/W R/W R/W Description Reserved This bit is always read as 0. Clock Output Selection Select a clock output from the TMOW pin when setting the TMOW bit in PMR3 to 1. 000: /4 010: /8 100: /16 110: /32 xx1: w 3 2 1 0 RCS3 RCS2 RCS1 RCS0 1 0 0 0 R/W R/W R/W R/W Clock Source Selection 0000: /8 Free running counter operation 0001: /32 Free running counter operation 0010: /128 Free running counter operation 0011: /256 Free running counter operation 0100: /512 Free running counter operation 0101: /2048 Free running counter operation 0110: /4096 Free running counter operation 0111: /8192 Free running counter operation 1000: w/4RTC operation 1001 to 1111: Setting prohibited Rev. 1.00 Dec. 18, 2006 Page 206 of 568 REJ09B0348-0100 Section 10 Realtime Clock (RTC) 10.3.8 RTC Interrupt Flag Register (RTCFLG) RTCFLG sets the corresponding flag when an interrupt occurs. Each flag is not cleared automatically even if the interrupt is accepted. To clear the flag, 0 should be written to the flag. Bit 7 Bit Name FOIFG Initial Value R/W R/W* Description [Setting condition] When a free running counter overflows [Clearing condition] 0 is written to FOIFG when FOIFG = 1 [Setting condition] When a week periodic interrupt occurs [Clearing condition] 0 is written to WKIFG when WKIFG = 1 [Setting condition] When a day periodic interrupt occurs [Clearing condition] 0 is written to DYIFG when DYIFG = 1 [Setting condition] When an hour periodic interrupt occurs [Clearing condition] 0 is written to HRIFG when HRIFG = 1 [Setting condition] When a minute periodic interrupt occurs [Clearing condition] 0 is written to MNIFG when MNIFG = 1 [Setting condition] When a one-second periodic interrupt occurs [Clearing condition] 0 is written to SEIFG when SEIFG = 1 [Setting condition] When a 0.5-second periodic interrupt occurs [Clearing condition] 0 is written to 05SEIFG when 05SEIFG = 1 [Setting condition] When a 0.25-second periodic interrupt occurs [Clearing condition] 0 is written to 025SEIFG when 025SEIFG = 1 6 WKIFG R/W* 5 DYIFG R/W* 4 HRIFG R/W* 3 MNIFG R/W* 2 SEIFG R/W* 1 05SEIFG R/W* 0 025SEIFG R/W* Note: * Only 0 can be written to clear the flag. Rev. 1.00 Dec. 18, 2006 Page 207 of 568 REJ09B0348-0100 Section 10 Realtime Clock (RTC) 10.4 10.4.1 Operation Initial Settings of Registers after Power-On The RTC registers that store second, minute, hour, and day-of week data are not reset by a RES input. Therefore, all registers must be set to their initial values after power-on. 10.4.2 Initial Setting Procedure Figure 10.3 shows the procedure for the initial setting of the RTC. To set the RTC again, also follow this procedure. RUN in RTCCR1 = 0 RST in RTCCR1 = 1 RST in RTCCR1 = 0 Set RTCCSR, RSECDR, RMINDR, RHRDR, RWKDR, 12/24 in RTCCR1, and PM RUN in RTCCR1 = 1 RTC operation is stopped. RTC registers and clock count controller are reset. Clock output and clock source are selected and second, minute, hour, day-of-week, operating mode, and a.m/p.m are set. RTC operation is started. Figure 10.3 Initial Setting Procedure Rev. 1.00 Dec. 18, 2006 Page 208 of 568 REJ09B0348-0100 Section 10 Realtime Clock (RTC) 10.4.3 Data Reading Procedure When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. Figure 10.4 shows an example in which correct data is not obtained. In this example, since only RSECDR is read after data update, about 1-minute inconsistency occurs. To avoid reading in this timing, the following processing must be performed. 1. Check the setting of the BSY bit, and when the BSY bit changes from 1 to 0, read from the second, minute, hour, and day-of-week registers. When about 62.5 ms is passed after the BSY bit is set to 1, the registers are updated, and the BSY bit is cleared to 0. 2. Making use of interrupts, read from the second, minute, hour, and day-of week registers after the corresponding flag of RTCFLG is set to 1 and the BSY bit is confirmed to be 0. 3. Read from the second, minute, hour, and day-of week registers twice in a row, and if there is no change in the read data, the read data is used. Before update BSY bit = 0 RWKDR = H'03, RHDDR = H'13, RMINDR = H'46, RSECDR = H'59 Processing flow (1) Day-of-week data register read (2) Hour data register read (3) Minute data register read H'03 H'13 H'46 BSY bit -> 1 (under data update) After update BSY bit -> 0 RWKDR = H'03, RHDDR = H'13, RMINDR = H'47, RSECDR = H'00 (4) Second data register read H'00 Figure 10.4 Example: Reading of Inaccurate Time Data Rev. 1.00 Dec. 18, 2006 Page 209 of 568 REJ09B0348-0100 Section 10 Realtime Clock (RTC) 10.5 Interrupt Sources There are eight kinds of RTC interrupts: a free-running counter overflow, week interrupt, day interrupt, hour interrupt, minute interrupt, one-second interrupt, 0.5-second interrupt, and 0.25second interrupt. When an interrupt request of the RTC occurs, the corresponding flag in RTCFLG is set to 1. When clearing the flag, write 0. Table 10.2 shows a interrupt sources. Table 10.2 Interrupt Sources Interrupt Name Overflow interrupt Week periodic interrupt Day periodic interrupt Hour periodic interrupt Minute periodic interrupt One-second periodic interrupt 0.5-second periodic interrupt 0.25-second periodic interrupt Interrupt Source Occurs when the free running counter is overflown. Interrupt Enable Bit FOIE Occurs every week when the day-of-week date WKIE register value becomes 0. Occurs every day when the day-of-week date register is counted. DYIE Occurs every hour when the hour date register HRIE is counted. Occurs every minute when the minute date register is counted. Occurs every second when the one-second date register is counted. Occurs every 0.5 seconds. Occurs every 0.25 seconds. MNIE 1SEIE 05SEIE 025SEIE Rev. 1.00 Dec. 18, 2006 Page 210 of 568 REJ09B0348-0100 Section 10 Realtime Clock (RTC) 10.6 10.6.1 Usage Notes Note on Clock Count The subclock must be connected to the 32.768-kHz resonator. When the 38.4-kHz resonator etc. is connected, the correct time count is not possible. 10.6.2 Note on Use of Interrupts Since the registers of the RTC are not cleared by a reset by the RES pin, power-on reset, or reset caused by WDT overflow, values after power-on are undefined. When using the RTC interrupt, these values have to be first initialized before setting the IENRTC bit in IENR1 to 1. Rev. 1.00 Dec. 18, 2006 Page 211 of 568 REJ09B0348-0100 Section 10 Realtime Clock (RTC) Rev. 1.00 Dec. 18, 2006 Page 212 of 568 REJ09B0348-0100 Section 11 Timer F Section 11 Timer F The timer F is a 16-bit timer having an output compare function. The timer F also provides for external event counting, and counter resetting, interrupt request generation, toggle output, etc., using compare match signals. Thus, it can be applied to various systems. The timer F can also be used as two independent 8-bit timers (timer FH and timer FL). Figure 11.1 shows a block diagram of the timer F. 11.1 Features * Choice of five counter input clocks Internal clocks (/32, /16, /4, and W/4) or external clocks can be selected. * Toggle output function Toggle output is performed to the TMOFH or TMOFL pin using a compare match signal. The initial value of toggle output can be set. * Counter resetting by a compare match signal * Two interrupt sources: One compare match, one overflow * Choice of 16-bit or 8-bit mode by settings of bits CKSH2 to CKSH0 in TCRF * Can operate in watch mode, subactive mode, and subsleep mode When W/4 is selected as an internal clock, the timer F can operate in watch mode, subactive mode, and subsleep mode. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 6.4, Module Standby Function.) Rev. 1.00 Dec. 18, 2006 Page 213 of 568 REJ09B0348-0100 Section 11 Timer F PSS IRRTFL TCRF W/4 TMIF TMOFL Toggle circuit TCFL Comparator OCRFL TCFH Toggle circuit TMOFH Comparator Match [Legend] TCRF: TCSRF: TCFH: TCFL: OCRFH: OCRFL: IRRTFH: IRRTFL: PSS: Timer control register F Timer control status register F 8-bit timer counter FH 8-bit timer counter FL Output compare register FH Output compare register FL Timer FH interrupt request flag Timer FL interrupt request flag Prescaler S OCRFH TCSRF IRRTFH Figure 11.1 Block Diagram of Timer F 11.2 Input/Output Pins Table 11.1 shows the input/output pins of the timer F. Table 11.1 Pin Configuration Name Timer F event input Timer FH output Timer FL output Abbreviation TMIF TMOFH TMOFL I/O Input Output Output Function Event input pin to TCFL Timer FH toggle output pin Timer FL toggle output pin Rev. 1.00 Dec. 18, 2006 Page 214 of 568 REJ09B0348-0100 Internal data bus Section 11 Timer F 11.3 Register Descriptions The timer F has the following registers. * * * * Timer counters FH and FL (TCFH, TCFL) Output compare registers FH and FL (OCRFH, OCRFL) Timer control register F (TCRF) Timer control/status register F (TCSRF) Timer Counters FH and FL (TCFH, TCFL) 11.3.1 TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters TCFH and TCFL. In addition to the use of TCF as a 16-bit counter with TCFH as the upper 8 bits and TCFL as the lower 8 bits, TCFH and TCFL can also be used as independent 8-bit counters. TCFH and TCFL are initialized to H'00 upon a reset. (1) 16-Bit Mode (TCF) When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input clock is selected by bits CKSL2 to CKSL0 in TCRF. TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF. When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in TCSRF is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an interrupt request is sent to the CPU. (2) 8-Bit Mode (TCFH/TCFL) When CKSH2 is set to 1 in TCRF, TCFH and TCFL operate as two independent 8-bit counters. The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to CKSL0) in TCRF. TCFH (TCFL) can be cleared in the event of a compare match by means of CCLRH (CCLRL) in TCSRF. When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF. If OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and if IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU. Rev. 1.00 Dec. 18, 2006 Page 215 of 568 REJ09B0348-0100 Section 11 Timer F 11.3.2 Output Compare Registers FH and FL (OCRFH, OCRFL) OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers. (1) 16-Bit Mode (OCRF) When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents are constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. At the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU. Toggle output can be provided from the TMOFH pin by means of compare matches, and the output level can be set by means of the TOLH bit in TCRF. (2) 8-Bit Mode (OCRFH/OCRFL) When CKSH2 is set to 1 in TCRF, OCRFH and OCRFL operate as two independent 8-bit registers. OCRFH contents are compared with TCFH, and OCRFL contents are with TCFL. When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is set to 1 in TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH (IENTFL) in IENR2 is 1 at this time, an interrupt request is sent to the CPU. Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare matches, and the output level can be set by means of the TOLH (TOLL) bit in TCRF. Rev. 1.00 Dec. 18, 2006 Page 216 of 568 REJ09B0348-0100 Section 11 Timer F 11.3.3 Timer Control Register F (TCRF) TCRF switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources, and selects the output level of the TMOFH and TMOFL pins. Bit 7 Bit Name TOLH Initial Value 0 R/W W Description Toggle Output Level H Sets the TMOFH pin output level. 0: Low level 1: High level Clock Select H Select the clock input to TCFH from among four internal clock sources or TCFL overflow. 000: 16-bit mode, counting on TCFL overflow signal 001: 16-bit mode, counting on TCFL overflow signal 010: 16-bit mode, counting on TCFL overflow signal 011: Using prohibited 100: 8-bit mode, counting on /32 101: 8-bit mode, counting on /16 110: 8-bit mode, counting on /4 111: 8-bit mode, counting on W/4 3 TOLL 0 W Toggle Output Level L Sets the TMOFL pin output level. 0: Low level 1: High level 6 5 4 CKSH2 CKSH1 CKSH0 0 0 0 W W W Rev. 1.00 Dec. 18, 2006 Page 217 of 568 REJ09B0348-0100 Section 11 Timer F Bit 2 1 0 Bit Name CKSL2 CKSL1 CKSL0 Initial Value 0 0 0 R/W W W W Description Clock Select L Select the clock input to TCFL from among four internal clock sources or external event input. 000: Counting on a rising or falling edge of an external event (TMIF pin)* 001: Counting on a rising or falling edge of an external event (TMIF pin)* 010: Counting on a rising or falling edge of an external event (TMIF pin)* 011: Using prohibited 100: Internal clock: counting on /32 101: Internal clock: counting on /16 110: Internal clock: counting on /4 111: Internal clock: counting on W/4 Note: * The TMIFEG bit in IEGR selects which edge of an external event is used for counting. 11.3.4 Timer Control/Status Register F (TCSRF) TCSRF performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests. Bit 7 Bit Name OVFH Initial Value 0 R/W R/W* Description Timer Overflow Flag H [Setting condition] When TCFH overflows from H'FF to H'00 [Clearing condition] When this bit is written to 0 after reading OVFH = 1 6 CMFH 0 R/W* Compare Match Flag H This is a status flag indicating that TCFH has matched OCRFH. [Setting condition] When the TCFH value matches the OCRFH value [Clearing condition] When this bit is written to 0 after reading CMFH = 1 Rev. 1.00 Dec. 18, 2006 Page 218 of 568 REJ09B0348-0100 Section 11 Timer F Bit 5 Bit Name OVIEH Initial Value 0 R/W R/W Description Timer Overflow Interrupt Enable H Selects enabling or disabling of interrupt generation when TCFH overflows. 0: TCFH overflow interrupt request is disabled 1: TCFH overflow interrupt request is enabled 4 CCLRH 0 R/W Counter Clear H In 16-bit mode, this bit selects whether TCF is cleared when TCF and OCRF match. In 8-bit mode, this bit selects whether TCFH is cleared when TCFH and OCRFH match. In 16-bit mode: 0: TCF clearing by compare match is disabled 1: TCF clearing by compare match is enabled In 8-bit mode: 0: TCFH clearing by compare match is disabled 1: TCFH clearing by compare match is enabled 3 OVFL 0 R/W* Timer Overflow Flag L This is a status flag indicating that TCFL has overflowed. [Setting condition] When TCFL overflows from H'FF to H'00 [Clearing condition] When this bit is written to 0 after reading OVFL = 1 2 CMFL 0 R/W* Compare Match Flag L This is a status flag indicating that TCFL has matched OCRFL. [Setting condition] When the TCFL value matches the OCRFL value [Clearing condition] When this bit is written to 0 after reading CMFL = 1 Rev. 1.00 Dec. 18, 2006 Page 219 of 568 REJ09B0348-0100 Section 11 Timer F Bit 1 Bit Name OVIEL Initial Value 0 R/W R/W Description Timer Overflow Interrupt Enable L Selects enabling or disabling of interrupt generation when TCFL overflows. 0: TCFL overflow interrupt request is disabled 1: TCFL overflow interrupt request is enabled 0 CCLRL 0 R/W Counter Clear L Selects whether TCFL is cleared when TCFL and OCRFL match. 0: TCFL clearing by compare match is disabled 1: TCFL clearing by compare match is enabled Note: * Only 0 can be written to clear the flag. 11.4 Operation The timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is constantly compared with the value set in the output compare register F, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. The timer F can also be used as two independent 8-bit timers. 11.4.1 Timer F Operation The timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in each of these modes is described below. (1) Operation in 16-Bit Timer Mode When the CKSH2 bit is cleared to 0 in TCRF, the timer F operates as a 16-bit timer. Following a reset, TCF is initialized to H'0000, OCRF to H'FFFF, and TCRF and TCSRF to H'00. The counter is incremented by an input signal from an external event (TMIF pin). The TMIFEG bit in IEGR selects which edge of an external event is used for counting. The timer F operating clock can be selected from internal clocks or external events according to settings of bits CKSL2 to CKSL0 in TCRF. OCRF contents are constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU, and at Rev. 1.00 Dec. 18, 2006 Page 220 of 568 REJ09B0348-0100 Section 11 Timer F the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF is cleared. The output level of the TMOFH pin can be set by the TOLH bit in TCRF. When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in TCSRF and IENTFH in IENR2 are both 1, an interrupt request is sent to the CPU. (2) Operation in 8-Bit Timer Mode When CKSH2 is set to 1 in TCRF, TCF operates as two independent 8-bit timers, TCFH and TCFL. The TCFH/TCFL input clock is selected by CKSH2 to CKSH0/CKSL2 to CKSL0 in TCRF. When the OCRFH/OCRFL and TCFH/TCFL values match, CMFH/CMFL is set to 1 in TCSRF. If IENTFH/IENTFL in IENR2 is 1, an interrupt request is sent to the CPU, and at the same time, TMOFH pin/TMOFL pin output is toggled. If CCLRH/CCLRL in TCSRF is 1, TCFH/TCFL is cleared. The output level of the TMOFH pin/TMOFL pin can be set by TOLH/TOLL in TCRF. When TCFH/TCFL overflows from H'FF to H'00, OVFH/OVFL is set to 1 in TCSRF. If OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request is sent to the CPU. 11.4.2 (1) TCF Increment Timing Internal Clock Operation TCF is incremented by internal clock or external event input. Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of internal clock sources (/32, /16, /4, or W/4) created by dividing the system clock ( or W). (2) External Event Operation When the CKSL2 bit in TCRF is cleared to 0, external event input is selected. The counter is incremented at both rising and falling edges of external events. The TMIFEG bit in IEGR selects which edge of an external event is used for counting. The external event pulse width requires clock time longer than 2 system clocks (), or 2 subclocks (SUB), depending on the operating mode. Note that an external event does not operate correctly with the lower pulse width. Rev. 1.00 Dec. 18, 2006 Page 221 of 568 REJ09B0348-0100 Section 11 Timer F 11.4.3 TMOFH/TMOFL Output Timing In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is toggled by the occurrence of a compare match. Figure 11.2 shows the output timing. TMIF (TMIFEG = 1) Count input clock TCF N N+1 N N+1 OCRF Compare match signal N N TMOFH, TMOFL Figure 11.2 TMOFH/TMOFL Output Timing 11.4.4 TCF Clear Timing TCF can be cleared by a compare match with OCRF. 11.4.5 Timer Overflow Flag (OVF) Set Timing OVF is set to 1 when TCF overflows from H'FFFF to H'0000. Rev. 1.00 Dec. 18, 2006 Page 222 of 568 REJ09B0348-0100 Section 11 Timer F 11.4.6 Compare Match Flag Set Timing The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match. The compare match signal is generated in the last state during which the values match (when TCF is updated from the matching value to a new value). When TCF matches OCRF, the compare match signal is not generated until the next counter clock. 11.5 Timer F Operating States The timer F operating states are shown in table 11.2. Table 11.2 Timer F Operating States Operating Mode TCF Reset Reset Active Functions* Sleep Functions* Watch Functions/ Halted* Sub-active Sub-sleep Standby Functions/ Halted* Functions Functions Functions Functions/ Halted* Retained Retained Retained Retained Retained Retained Halted Module Standby Halted OCRF TCRF TCSRF Reset Reset Reset Functions Functions Functions Retained Retained Retained Retained Retained Retained Retained Retained Retained Note: * When W/4 is selected as the TCF internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. This results in a maximum count cycle error of 1/ (s). When the counter is operated in subactive mode, watch mode, or subsleep mode, W /4 must be selected as the internal clock. The counter will not operate if any other internal clock is selected. Rev. 1.00 Dec. 18, 2006 Page 223 of 568 REJ09B0348-0100 Section 11 Timer F 11.6 Usage Notes The following types of contention and operation can occur when the timer F is used. 11.6.1 16-Bit Timer Mode In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal is generated. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the TMOFL pin should be used as a port pin. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, even if the written data and the counter value match, a compare match signal will not necessarily be generated at that point. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped. Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated. Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied. When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not output. 11.6.2 (1) 8-Bit Timer Mode TCFH, OCRFH In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write. If an OCRFH write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, even if the written data and the counter value match, a compare match signal will not necessarily be generated at that point. The compare match signal is output in synchronization with the TCFH clock. If a TCFH write and overflow signal output occur simultaneously, the overflow signal is not output. Rev. 1.00 Dec. 18, 2006 Page 224 of 568 REJ09B0348-0100 Section 11 Timer F (2) TCFL, OCRFL In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLL data is output to the TMOFL pin as a result of the TCRF write. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, even if the written data and the counter value match, a compare match signal will not necessarily be generated at that point. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped. If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not output. 11.6.3 Flag Clearing When W/4 is selected as the internal clock, "Interrupt source generation signal" will be operated with W and the signal will be outputted with W width. And, "Overflow signal" and "Compare match signal" are controlled with 2 cycles of W signals. Those signals are output with 2-cycle width of W (figure 11.3) In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the term of validity of "Interrupt source generation signal", same interrupt request flag is set. (1 in figure 11.3) And, the timer overflow flag and compare match flag cannot be cleared during the term of validity of "Overflow signal" and "Compare match signal". For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time timer FH, timer FL interrupt might be repeated. (2 in figure 11.3) Therefore, to definitely clear interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and compare match flag, clear should be processed after read timer control status register F (TCSRF) after the time that calculated with below (1) formula. For ST of (1) formula, please substitute the longest number of execution states in used instruction. In subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and compare match flag clear. Rev. 1.00 Dec. 18, 2006 Page 225 of 568 REJ09B0348-0100 Section 11 Timer F The term of validity of "Interrupt source generation signal" = 1 cycle of W + waiting time for completion of executing instruction + interrupt time synchronized with = 1/W + ST x (1/) + (2/) (second).....(1) ST: Executing number of execution states Method 1 is recommended to operate for time efficiency. Method 1 1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0). 2. After program process returned normal handling, clear interrupt request flags (IRRTFH, IRRTFL) after more than that calculated with (1) formula. 3. After reading the timer control status register F (TCSRF), clear the timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL). 4. Enable interrupts (set IENFH, IENFL to 1). Method 2 1. Set interrupt handling routine time to more than time that calculated with (1) formula. 2. Clear interrupt request flags (IRRTFH, IRRTFL) at the end of interrupt handling routine. 3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL). All above attentions are also applied in 16-bit mode and 8-bit mode. Rev. 1.00 Dec. 18, 2006 Page 226 of 568 REJ09B0348-0100 Section 11 Timer F Interrupt request flag clear 2 Interrupt request flag clear Program processing Interrupt Interrupt Normal W Interrupt source generation signal (internal signal, nega-active) Overflow signal, compare match signal (internal signal, nega-active) Interrupt request flag (IRRTFH, IRRTFL) 1 Figure 11.3 Clear Interrupt Request Flag when Interrupt Source Generation Signal is Valid 11.6.4 Timer Counter (TCF) Read/Write When W/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on TCF is impossible. And when reading TCF, as the system clock and internal clock are mutually asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF read value error of 1. When reading or writing TCF in active (high-speed, medium-speed) mode is needed, please select the internal clock except for W/4 before read/write is performed. In subactive mode, even if W /4 is selected as the internal clock, TCF can be read from or written to normally. Rev. 1.00 Dec. 18, 2006 Page 227 of 568 REJ09B0348-0100 Section 11 Timer F Rev. 1.00 Dec. 18, 2006 Page 228 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Section 12 16-Bit Timer Pulse Unit (TPU) Microcontrollers of the H8/38776 Group have an on-chip 16-bit timer pulse unit (TPU) comprised of two 16-bit timer channels. The function list of the TPU is shown in table 12.1. A block diagram of the TPU is shown in figure 12.1. 12.1 Features * Maximum 4-pulse input/output * Selection of 7 or 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register synchronous input/output is possible by synchronous counter operation PWM output with any duty level is possible A maximum 2-phase PWM output is possible in combination with synchronous operation * Operation with cascaded connection * Fast access via internal 16-bit bus * 6-type interrupt sources * Register data can be transmitted automatically * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 6.4, Module Standby Function.) Rev. 1.00 Dec. 18, 2006 Page 229 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.1 TPU Functions Item Count clock Channel 1 /1 /4 /16 /64 /256 TCLKA TCLKB General registers (TGR) I/O pins Counter clear function Compare match output 0 output TIOCA TIOCB 1 output TIOCA TIOCB Toggle output Input capture function Synchronous operation PWM mode Interrupt sources TIOCA TIOCB TGRA_1 TGRB_1 TIOCA1 TIOCB1 TGR compare match or input capture Possible Possible Possible Possible Possible Possible 3 sources * * * Compare match or input capture 1A Compare match or input capture 1B Overflow Channel 2 /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 TIOCA2 TIOCB2 TGR compare match or input capture Possible Possible Possible Possible Possible Possible 3 sources * * * Compare match or input capture 2A Compare match or input capture 2B Overflow Rev. 1.00 Dec. 18, 2006 Page 230 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Clock input Internal clock: /1 /4 /16 /64 /256 /1024 TCLKA TCLKB TCLKC TSYR Control logic Internal data bus TMDR Channel 2 TSR TSTR External clock: Common TGRA Control logic for channels 1 and 2 TIOR TIER TCR Input/output pins Channel 1: Channel 2: TIOCA1 TIOCA2 Module data bus TGRB TCNT Bus interface TGRA TIOR [Legend] TSTR: Timer start register TSYR: Timer synchro register TCR: Timer control register TMDR: Timer mode register TCNT: Timer counter Timer I/O control registers TIOR: Timer interrupt enable register TIER: Timer status register TSR: TGR (A, B): TImer general registers (A, B) Figure 12.1 Block Diagram of TPU 12.2 Input/Output Pins Table 12.2 Pin Configuration Channel Common Symbol TCLKA TCLKB TCLKC 1 TIOCA1 TIOCB1 2 TIOCA2 TIOCB2 I/O Input Input Input I/O Input I/O Input Function External clock A input pin External clock B input pin External clock C input pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input pin TIER TCR Channel 1: Channel 2: TIOCB1 TIOCB2 Rev. 1.00 Dec. 18, 2006 Page 231 of 568 REJ09B0348-0100 TGRB TCNT Input pins Interrupt request signals Channel 1: TGI1A TGI1B TCI1V Channel 2: TGI2A TGI2B TCI2V TMDR Channel 1 TSR Section 12 16-Bit Timer Pulse Unit (TPU) 12.3 Register Descriptions The TPU has the following registers for each channel. Channel 1: * * * * * * * * Timer control register_1 (TCR_1) Timer mode register_1 (TMDR_1) Timer I/O control register_1 (TIOR_1) Timer interrupt enable register_1 (TIER_1) Timer status register_1 (TSR_1) Timer counter_1 (TCNT_1) Timer general register A_1 (TGRA_1) Timer general register B_1 (TGRB_1) Channel 2: * * * * * * * * Timer control register_2 (TCR_2) Timer mode register_2 (TMDR_2) Timer I/O control register_2 (TIOR_2) Timer interrupt enable register_2 (TIER_2) Timer status register_2 (TSR_2) Timer counter_2 (TCNT_2) Timer general register A_2 (TGRA_2) Timer general register B_2 (TGRB_2) Common: * Timer start register (TSTR) * Timer synchro register (TSYR) Rev. 1.00 Dec. 18, 2006 Page 232 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.3.1 Timer Control Register (TCR) TCR controls TCNT operation for each channel. The TPU has a total of two TCR registers, one for each channel. TCR should be set when TCNT operation is stopped. Bit 7 6 5 4 3 Bit Name CCLR1 CCLR0 CKEG1 CKEG0 Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved This bit is always read as 0 and cannot be modified. Counter Clear 1 and 0 These bits select the TCNT counter clearing source. See table 12.3 for details. Clock Edge 1 and 0 These bits select the input clock edge. When the internal clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). Internal clock edge selection is valid when the input clock is /4 or slower. If the input clock is /1, this setting is ignored and count at a rising edge is selected. 00: Count at rising edge 01: Count at falling edge 1X: Count at both edges [Legend] X: Don't care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Timer Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables12.4 and 12.5 for details. Rev. 1.00 Dec. 18, 2006 Page 233 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.3 CCLR1 and CCLR0 (Channels 1 and 2) Channel 1, 2 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation is selected by setting the SYNC bit in TSYR to 1. Table 12.4 TPSC2 to TPSC0 (Channel 1) Bit 2 Channel TPSC2 1 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on /256 Counts on TCNT_2 overflow Rev. 1.00 Dec. 18, 2006 Page 234 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.5 TPSC2 to TPSC0 (Channel 2) Bit 2 Channel TPSC2 2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 12.3.2 Timer Mode Register (TMDR) TMDR sets the operating mode for each channel. The TPU has a total of two TMDR registers, one for each channel. TMDR should be set when TCNT operation is stopped. Bit 7, 6 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 5, 4 All 0 Reserved These bits are always read as 0 and cannot be modified. 3, 2 1 0 MD1 MD0 All 0 0 0 R/W R/W Reserved The write value should always be 0. Modes 1 and 0 These bits set the timer operating mode. See table 12.6 for details. Rev. 1.00 Dec. 18, 2006 Page 235 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.6 MD3 to MD0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 Description Normal operation Reserved PWM mode 1 PWM mode 2 12.3.3 Timer I/O Control Register (TIOR) TIOR controls TGR. The TPU has a total of two TIOR registers, one for each channel. Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. * TIOR_1, TIOR_2 Bit 7 6 5 4 3 2 1 0 Bit Name IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 All 0 Initial Value All 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Control A3 to A0 Specify the function of TGRA. For details, refer to tables 12.9 and 12.10. Description I/O Control B3 to B0 Specify the function of TGRB. For details, refer to tables 12.7 and 12.8. Rev. 1.00 Dec. 18, 2006 Page 236 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.7 TIOR_1 (Channel 1) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 [Legend] x: Don't care x x x Input capture Capture input source is TIOCB1 pin register Input capture at rising edge Capture input source is TIOCB1 pin Input capture at falling edge Capture input source is TIOCB1 pin Input capture at both edges Setting prohibited TGRB_1 Function Output compare register TIOCB1 Pin Function Output disabled Setting prohibited Rev. 1.00 Dec. 18, 2006 Page 237 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.8 TIOR_2 (Channel 2) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 [Legend] x: Don't care x Input capture Capture input source is TIOCB2 pin register Input capture at rising edge Capture input source is TIOCB2 pin Input capture at falling edge Capture input source is TIOCB2 pin Input capture at both edges TGRB_2 Function Output compare register TIOCB2 Pin Function Output disabled Setting prohibited Rev. 1.00 Dec. 18, 2006 Page 238 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.9 TIOR_1 (Channel 1) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 [Legend] x: Don't care x x x Input capture register TGRA_1 Function Output compare register TIOCA1 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCA1 pin Input capture at rising edge Capture input source is TIOCA1 pin Input capture at falling edge Capture input source is TIOCA1 pin Input capture at both edges Setting prohibited Rev. 1.00 Dec. 18, 2006 Page 239 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.10 TIOR_2 (Channel 2) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 [Legend] x: Don't care x TGRA_2 Function Output compare register TIOCA2 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is TIOCA2 pin register Input capture at rising edge Capture input source is TIOCA2 pin Input capture at falling edge Capture input source is TIOCA2 pin Input capture at both edges Rev. 1.00 Dec. 18, 2006 Page 240 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.3.4 Timer Interrupt Enable Register (TIER) TIER controls enabling or disabling of interrupt requests for each channel. The TPU has a total of two TIER registers, one for each channel. Bit 7 6 5 4 Bit Name TCIEV Initial Value 0 1 0 0 R/W R/W R/W Description Reserved This bit is readable/writable. Reserved This bit is always read as 1 and cannot be modified. Reserved The write value should always be 0. Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3, 2 All 0 Reserved These bits are always read as 0 and cannot be modified. 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Rev. 1.00 Dec. 18, 2006 Page 241 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.3.5 Timer Status Register (TSR) TSR indicates the status for each channel. The TPU has a total of two TSR registers, one for each channel. Bit 7, 6 5 4 Bit Name TCFV Initial Value All 1 0 0 R/W Description Reserved These bits are always read as 1 and cannot be modified. Reserved This bit is always read as 0 and cannot be modified. R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 3, 2 1 TGFB All 0 0 Reserved These bits are always read as 0 and cannot be modified. R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] * * When TCNT = TGRB and TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register When 0 is written to TGFB after reading TGFB = 1 [Clearing condition] * Rev. 1.00 Dec. 18, 2006 Page 242 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Bit 0 Bit Name TGFA Initial value 0 R/W Description R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] * * When TCNT = TGRA and TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register When 0 is written to TGFA after reading TGFA = 1 [Clearing condition] * Note: * Only 0 can be written to clear the flag. 12.3.6 Timer Counter (TCNT) TCNT is a 16-bit readable/writable counter. The TPU has a total of two TCNT counters, one for each channel. TCNT is initialized to H'0000 by a reset or in hardware standby mode. TCNT cannot be accessed in 8-bit units; it must always be accessed in 16-bit units. 12.3.7 Timer General Register (TGR) TGR is a 16-bit readable/writable register, functioning as either output compare or input capture register. The TPU has a total of four TGR registers, two for each channel. TGR is initialized to H'FFFF by a reset. TGR cannot be accessed in 8-bit units; it must always be accessed in 16-bit units. Rev. 1.00 Dec. 18, 2006 Page 243 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.3.8 Timer Start Register (TSTR) TSTR selects TCNT operation/stoppage for channels 1 and 2. TCNT starts counting for channel in which the corresponding bit is set to 1. When setting the operating mode in TMDR or setting the TCNT count clock in TCR, first stop the TCNT operation. Bit 7 to 3 2 1 Bit Name CST2 CST1 Initial Value All 0 0 0 R/W R/W R/W Description Reserved The write value should always be 0. Counter Start 2 and 1 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the output compare output level of the TIOC pin is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_n count operation is stopped 1: TCNT_n performs count operation (n = 2 or 1) 0 0 Reserved The write value should always be 0. Rev. 1.00 Dec. 18, 2006 Page 244 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.3.9 Timer Synchro Register (TSYR) TSYR selects independent operation or synchronous operation of TCNT for each channel. Synchronous operation is performed for channel in which the corresponding bit in TSYR is set to 1. Bit 7 to 3 2 1 Bit Name SYNC2 SYNC1 Initial Value All 0 0 0 R/W R/W R/W Description Reserved The write value should always be 0. Timer Synchro 2 and 1 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR1 and CCLR0 in TCR. 0: TCNT_n operates independently (TCNT presetting/ clearing is unrelated to other channels) 1: TCNT_n performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible (n = 2 or 1) 0 0 Reserved The write value should always be 0. Rev. 1.00 Dec. 18, 2006 Page 245 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.4 12.4.1 Interface to CPU 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the CPU is 16 bits wide, these registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 12.2. Internal data bus H CPU L Bus interface Module data bus TCNTH TCNTL Figure 12.2 16-Bit Register Access Operation [CPU TCNT (16 Bits)] 12.4.2 8-Bit Registers Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. Examples of 8-bit register access operation are shown in figure 12.3, 12.4, and 12.5. Internal data bus H CPU L Bus interface Module data bus TCR Figure 12.3 8-Bit Register Access Operation [CPU TCR (Upper 8 Bits)] Rev. 1.00 Dec. 18, 2006 Page 246 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Internal data bus H CPU L Bus interface Module data bus TMDR Figure 12.4 8-Bit Register Access Operation [CPU TMDR (Lower 8 Bits)] Internal data bus H CPU L Bus interface Module data bus TCR TMDR Figure 12.5 8-Bit Register Access Operation [CPU TCR and TMDR (16 Bits)] Rev. 1.00 Dec. 18, 2006 Page 247 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.5 12.5.1 Operation Basic Functions Each channel has TCNT and TGR. TCNT performs up-counting, and is also capable of freerunning operation, periodic counting, and external event counting. TGR can be used as an input capture register or output compare register. (1) Counter Operation When one of bits CST1 and CST2 is set to 1 in TSTR, TCNT for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. (a) Example of Count Operation Setting Procedure Figure 12.6 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select TGR to be used as the TCNT clearing source with bits CCLR1 and CCLR0 in TCR. [3] Designate TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in TGR selected in [2]. [5] Set the CST bit in TSTR to 1 to start the counter operation. Operation selection Select counter clock [1] Periodic counter Free-running counter Select counter clearing source [2] [3] Select output compare register Set period [4] Start count operation [5] Start count operation Figure 12.6 Example of Counter Operation Setting Procedure Rev. 1.00 Dec. 18, 2006 Page 248 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) (b) Free-Running Count Operation and Periodic Count Operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 12.7 illustrates free-running counter operation. TCNT value H'FFFF H'0000 CST bit TCFV Time Figure 12.7 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, TCNT for the relevant channel performs periodic count operation. TGR for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 and CCLR1 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 12.8 illustrates periodic counter operation. Rev. 1.00 Dec. 18, 2006 Page 249 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) TCNT value TGR Counter cleared by TGR compare match H'0000 CST bit TGF Time Flag cleared by software Figure 12.8 Periodic Counter Operation (2) Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. (a) Example of Setting Procedure for Waveform Output by Compare Match Figure 12.9 shows an example of the setting procedure for waveform output by compare match. [1] Select 0 output or 1 output for initial value, and 0 output, 1 output, or toggle output, by for compare match output value means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation. Input selection [1] Select waveform output mode [2] Set output timing [3] Start count operation < Waveform output > Figure 12.9 Example of Setting Procedure for Waveform Output by Compare Match (b) Examples of Waveform Output Operation Figure 12.10 shows an example of 1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A. When the set level and the pin level match, the pin level does not change. Rev. 1.00 Dec. 18, 2006 Page 250 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) TCNT value H'FFFF TGRA H'0000 No change No change 1 output Time TIOCA Figure 12.10 Example of 0 Output/1 Output Operation Figure 12.11 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match A), and settings have been made such that the output is toggled by compare match A. TCNT value Counter cleared by TGRA compare match H'FFFF TGRA H'0000 Time Toggle output TIOCA Figure 12.11 Example of Toggle Output Operation (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. (a) Example of Input Capture Operation Setting Procedure Figure 12.12 shows an example of the setting procedure for input capture operation. Rev. 1.00 Dec. 18, 2006 Page 251 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Input selection Select input capture input [1] Designate TGR as an input capture register by means of TIOR, and select the input capture source and, rising edge, falling edge, or both edges as the input signal edge. [1] [2] Set the CST bit in TSTR to 1 to start the count operation. [2] Start count Figure 12.12 Example of Setting Procedure for Input Capture Operation (b) Example of Input Capture Operation Figure 12.13 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the input capture input edge of the TIOCA pin, the falling edge has been selected as the input capture input edge of the TIOCB pin, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 12.13 Example of Input Capture Operation Rev. 1.00 Dec. 18, 2006 Page 252 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.5.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Synchronous operation can be set for each channel. (1) Example of Synchronous Operation Setting Procedure Figure 12.14 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing source generation channel? Yes Select counter clearing source Start count No [3] Set synchronous counter clearing Start count [4] [5] [5] [1] Set 1 to the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR1 and CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR1 and CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set 1 to the CST bits in TSTR for the relevant channels, to start the count operation. Figure 12.14 Example of Synchronous Operation Setting Procedure Rev. 1.00 Dec. 18, 2006 Page 253 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) (2) Example of Synchronous Operation Figure 12.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 1 and 2, TGRB_1 compare match has been set as the channel 1 counter clearing source, and synchronous clearing has been set for the channel 2 counter clearing source. Two-phase PWM waveforms are output from pins TIOC1A and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_1 compare match, are performed for channel 1 and 2 TCNT counters, and the data set in TGRB_1 is used as the PWM cycle. For details on PWM modes, see section 12.5.4, PWM Modes. Synchronous clearing by TGRB_1 compare match TCNT_1 and TCNT_2 TGRB_1 TGRB_2 TGRA_1 TGRA_2 H'0000 Time TIOCA1 TIOCA2 Figure 12.15 Example of Synchronous Operation Rev. 1.00 Dec. 18, 2006 Page 254 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.5.3 Operation with Cascaded Connection Operation as a 32-bit counter can be performed by cascading two 16-bit counter channels. This function is enabled when the TPSC2 to TPSC0 bits in TCR are set to count on TCNT2 overflow for the channel 1 counter clock. Table 12.11 shows the counter combination used in operation with the cascaded connection. Table 12.11 Counter Combination in Operation with Cascaded Connection Combination Channel 1 and channel 2 Upper 16 bits TCNT1 Lower 16 bits TCNT2 (1) Setting Procedure for Operation with Cascaded Connection Figure 12.16 shows the setting procedure for cascaded connection operation. Operation with cascaded connection Set operation with cascaded connection [1] Set bits TPSC2 to TPSC0 in TCR in channel 1 to B'111 to select to count on TCNT2 overflow. [1] [2] Set 1 to the CST bit in TSTR corresponding the upper and lower channels to start counting. Start count [2] Figure 12.16 Setting Procedure for Operation with Cascaded Operation Rev. 1.00 Dec. 18, 2006 Page 255 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) (2) Example of Operation with Cascaded Connection Figure 12.17 shows an example of operation with cascaded connection, where TCNT1 is set to count TCNT2 overflow, TCRA_1 and TCRA_2 are set to be input capture registers, and the TIOC pin rising edge is selected. If rising edges are input simultaneously to the TIOCA1 and TIOCA2 pins, the upper 16 bits of 32bit data are transferred to TGRA_1 and the lower 16 bits are transferred to TGRA_2. TCNT1 clock TCNT1 TCNT2 clock H'03A1 H'03A2 TCNT2 H'FFFF H'0000 H'0001 TIOCA1 TIOCA2 TGRA_1 H'03A2 TGRA_2 H'0000 Figure 12.17 Example of Operation with Cascaded Connection Rev. 1.00 Dec. 18, 2006 Page 256 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.5.4 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. (1) PWM Mode 1 PWM output is generated from the TIOCA pin by pairing TGRA with TGRB. The level specified by bits IOA0 to IOA3 in TIOR is output from the TIOCA pin at compare match A, and the level specified by bits IOB0 to IOB3 in TIOR is output at compare match B. The initial output value is the value set in TGRA. If the set values of paired TGRs are identical, the output value does not change even if a compare match occurs. In PWM mode 1, PWM output is enabled up to 2 phases. (2) PWM Mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change even if a compare match occurs. In PWM mode 2, PWM output is enabled up to two phases. The correspondence between PWM output pins and registers is shown in table 12.12. Rev. 1.00 Dec. 18, 2006 Page 257 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Table 12.12 PWM Output Registers and Output Pins Output Pins Channel 1 Registers TGRA_1 TGRB_1 2 Note: * TGRA_2 TGRB_2 TIOCA2 PWM Mode 1 TIOCA1 PWM Mode 2* TIOCA1 TIOCA2 In PWM mode 2, PWM output is not possible for TGR in which the period is set. (3) Example of PWM Mode Setting Procedure Figure 12.18 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] Select counter clearing source [2] Select waveform output level [3] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR1 and CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 start the count operation. Set TGR [4] Set PWM mode [5] Start count [6] Figure 12.18 Example of PWM Mode Setting Procedure Rev. 1.00 Dec. 18, 2006 Page 258 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) (4) Examples of PWM Mode Operation Figure 12.19 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB are used as the duty levels. TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 12.19 Example of PWM Mode Operation (1) Figure 12.20 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 1 and 2, TGRB_2 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_1, TGRB_1, and TGRA_2), outputting a two-phase PWM waveform. In this case, the value set in TGRB_2 is used as the cycle, and the values set in the other TGRs are used as the duty levels. Rev. 1.00 Dec. 18, 2006 Page 259 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Synchronous clearing by TGRB_2 compare match TCNT_1 and TCNT_2 TGRB_2 TGRA_2 TGRA_1 H'0000 Time TIOCA1 TIOCA2 Figure 12.20 Example of PWM Mode Operation (2) Rev. 1.00 Dec. 18, 2006 Page 260 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Figure 12.21 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB H'0000 TGRB rewritten TGRB rewritten Time TIOCA 0% duty TCNT value TGRB rewritten TGRA Output does not change when cycle register and duty register compare matches occur simultaneously TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time TIOCA TCNT value TGRB rewritten TGRA Output does not change when cycle register and duty register compare matches occur simultaneously TGRB rewritten TGRB H'0000 100% duty 0% duty TGRB rewritten Time TIOCA Figure 12.21 Example of PWM Mode Operation (3) Rev. 1.00 Dec. 18, 2006 Page 261 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.6 Interrupt Sources There are two kinds of TPU interrupt source; TGR input capture/compare match and TCNT overflow. Each interrupt source has its own status flag and enable/disable bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt source is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Channel priority can be changed by the interrupt controller, however the priority within a channel is fixed. For details, see section 4, Interrupt Controller. Table 12.13 lists the TPU interrupt sources. Table 12.13 TPU Interrupts Channel 1 Name TGI1A TGI1B TCI1V 2 TGI2A TGI2B TCI2V Interrupt Source TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow Interrupt Flag TGFA_1 TGFB_1 TCFV_1 TGFA_2 TGFB_2 TCFV_2 Low Priority High (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has a total of four input capture/compare match interrupts, two for each channel. (2) Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has a total of two overflow interrupts, one for each channel. Rev. 1.00 Dec. 18, 2006 Page 262 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.7 12.7.1 (1) Operation Timing Input/Output Timing TCNT Count Timing Figure 12.22 shows TCNT count timing in internal clock operation, and figure 12.23 shows TCNT count timing in external clock operation. Internal clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 12.22 Count Timing in Internal Clock Operation External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 12.23 Count Timing in External Clock Operation Rev. 1.00 Dec. 18, 2006 Page 263 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) (2) Output Compare Output Timing A compare match signal is generated in the last state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 12.24 shows output compare output timing. TCNT input clock N N+1 TCNT TGR N Compare match signal TIOC pin Figure 12.24 Output Compare Output Timing Rev. 1.00 Dec. 18, 2006 Page 264 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) (3) Input Capture Signal Timing Figure 12.25 shows input capture signal timing. Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 12.25 Input Capture Input Signal Timing (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 12.26 shows the timing when counter clearing on compare match is specified, and figure 12.27 shows the timing when counter clearing on input capture is specified. Compare match signal Counter clear signal TCNT N H'0000 TGR N Figure 12.26 Counter Clear Timing (Compare Match) Rev. 1.00 Dec. 18, 2006 Page 265 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Input capture signal Counter clear signal TCNT N H'0000 TGR N Figure 12.27 Counter Clear Timing (Input Capture) 12.7.2 (1) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 12.28 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. TCNT input clock TCNT N N+1 TGR Compare match signal TGF flag TGI interrupt N Figure 12.28 TGI Interrupt Timing (Compare Match) Rev. 1.00 Dec. 18, 2006 Page 266 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) (2) TGF Flag Setting Timing in Case of Input Capture Figure 12.29 shows the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing. Input capture signal TCNT N TGR TGF flag TGI interrupt N Figure 12.29 TGI Interrupt Timing (Input Capture) (3) TCFV Flag Setting Timing Figure 12.30 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. TCNT input clock TCNT (overflow) Overflow signal TCFV flag H'FFFF H'0000 TCIV interrupt Figure 12.30 TCIV Interrupt Setting Timing Rev. 1.00 Dec. 18, 2006 Page 267 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figure 12.31 shows the timing for status flag clearing by the CPU. TSR write cycle T2 T1 Address Write signal Status flag TSR address Interrupt request signal Figure 12.31 Timing for Status Flag Clearing by CPU 12.8 12.8.1 Usage Notes Module Standby Function Setting TPU operation can be disabled or enabled using the clock stop register. The initial setting is for the TPU to operate. Register access is enabled by clearing the module standby function. For details, refer to section 6.4, Module Standby Function. 12.8.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower pulse widths. Rev. 1.00 Dec. 18, 2006 Page 268 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.8.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the last state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where (N + 1) f: Counter frequency : Operating frequency N: TGR set value Contention between TCNT Write and Clear Operation 12.8.4 If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes priority and the TCNT write is not performed. Figure 12.32 shows the timing in this case. TCNT write cycle T1 T2 Address Write signal Counter clear signal TCNT N TCNT address H'0000 Figure 12.32 Contention between TCNT Write and Clear Operation Rev. 1.00 Dec. 18, 2006 Page 269 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.8.5 Contention between TCNT Write and Increment Operation If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes priority and TCNT is not incremented. Figure 12.33 shows the timing in this case. TCNT write cycle T1 T2 Address Write signal TCNT input clock TCNT N TCNT address M TCNT write data Figure 12.33 Contention between TCNT Write and Increment Operation Rev. 1.00 Dec. 18, 2006 Page 270 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.8.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes priority and the compare match signal is inhibited. A compare match does not occur even if the previous value is written. Figure 12.34 shows the timing in this case. TGR write cycle T1 T2 Address Write signal Compare match signal TCNT TGR N TGR address Inhibited N+1 N TGR write data M Figure 12.34 Contention between TGR Write and Compare Match Rev. 1.00 Dec. 18, 2006 Page 271 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.8.7 Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, data that is read will be data after input capture transfer. Figure 12.35 shows the timing in this case. TGR read cycle T2 T1 Address Read signal Input capture signal TGR Internal data bus X TGR address M M Figure 12.35 Contention between TGR Read and Input Capture Rev. 1.00 Dec. 18, 2006 Page 272 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.8.8 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes priority and the write to TGR is not performed. Figure 12.36 shows the timing in this case. TGR write cycle T2 T1 Address Write signal Input capture signal TCNT M M TGR address TGR Figure 12.36 Contention between TGR Write and Input Capture Rev. 1.00 Dec. 18, 2006 Page 273 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.8.9 Contention between Overflow and Counter Clearing If overflow and counter clearing occur simultaneously, the TCFV flag in TSR is not set and TCNT clearing takes priority. Figure 12.37 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. TCNT input clock TCNT Counter clear signal TGF TCFV Disabled H'FFFF H'0000 Figure 12.37 Contention between Overflow and Counter Clearing Rev. 1.00 Dec. 18, 2006 Page 274 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) 12.8.10 Contention between TCNT Write and Overflow If there is an up-count in the T2 state of a TCNT write cycle and overflow occurs, the TCNT write takes priority and the TCFV flag in TSR is not set. Figure 12.38 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T2 T1 Address Write signal TCNT TCFV flag H'FFFF M TCNT address TCNT write data Figure 12.38 Contention between TCNT Write and Overflow 12.8.11 Multiplexing of I/O Pins The TIOCA1 I/O pin is multiplexed with the TCLKA input pin, the TIOCB1 I/O pin with the TCLKB input pin, and the TIOCA2 I/O pin with the TCLKC input pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 12.8.12 Interrupts when Module Standby Function is Used If the module standby function is used when an interrupt has been requested, it will not be possible to clear the CPU interrupt source. Interrupts should therefore be disabled before using the module standby function. Rev. 1.00 Dec. 18, 2006 Page 275 of 568 REJ09B0348-0100 Section 12 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Dec. 18, 2006 Page 276 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) Section 13 Asynchronous Event Counter (AEC) The asynchronous event counter (AEC) is an event counter that is incremented by external event clock or internal clock input. Figure 13.1 shows a block diagram of the asynchronous event counter. 13.1 Features * Can count asynchronous events Can count external events input asynchronously without regard to the operation of system clocks () or subclocks (SUB). * Can be used as two-channel independent 8-bit event counter or single-channel independent 16bit event counter. * Event/clock input is enabled when IRQAEC goes high or event counter PWM output (IECPWM) goes high. * Both edge sensing can be used for IRQAEC or event counter PWM output (IECPWM) interrupts. When the asynchronous counter is not used, they can be used as independent interrupts. * When an event counter PWM is used, event clock input enabling/disabling can be controlled at a constant cycle. * Selection of four clock sources Three internal clocks (/2, /4, or /8) or external event can be selected. * Both edge counting is possible for the AEVL and AEVH pins. * Counter resetting and halting of the count-up function can be controlled by software. * Automatic interrupt generation on detection of an event counter overflow * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 6.4, Module Standby Function.) * The IRQAEC pin can select the on-chip oscillator and the system clock oscillator during a reset, though this function does not apply to a reset by the watchdog timer (supported only by the mask ROM version). Note: For the mask ROM version, the level on the IRQAEC pin determines whether the system clock is output from the on-chip oscillator or the system clock oscillator during resets other than those generated by the watchdog timer. If an initial design includes a flashROM-version LSI circuit with the IRQAEC pin fixed to Vcc, and the LSI circuit is then replaced by the masked ROM version with operation drivable by the on-chip oscillator, the IRQAEC pin has to be fixed to GND if the LSI circuit is still to be driven by the Rev. 1.00 Dec. 18, 2006 Page 277 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) system clock. Be sure to take this point into consideration. For details, see section 5.1.2, Oscillator Control Register (OSCCR). IRREC PSS ECCR ECCSR /2 /4, /8 ECH (8 bits) OVH AEVH Edge sensing circuit OVL CK AEVL IRQAEC Edge sensing circuit Edge sensing circuit To CPU interrupt (IRREC2) ECPWCR IECPWM PWM waveform generator /2, /4, /8, /16, /32, /64 AEGSR [Legend] ECPWCR: ECPWDR: AEGSR: ECCSR: Event counter PWM compare register Event counter PWM data register Input pin edge select register Event counter control/status register ECL: Event counter L ECCR: Event counter control register ECH: Event counter H ECPWDR Figure 13.1 Block Diagram of the Asynchronous Event Counter Rev. 1.00 Dec. 18, 2006 Page 278 of 568 REJ09B0348-0100 Internal data bus ECL (8 bits) CK Section 13 Asynchronous Event Counter (AEC) 13.2 Input/Output Pins Table 13.1 shows the pin configuration of the asynchronous event counter. Table 13.1 Pin Configuration Name Abbreviation I/O Input Input Input Function Event input pin for input to event counter H Event input pin for input to event counter L Input pin for interrupt enabling event input Input pin to select the on-chip oscillator and the system clock oscillator (supported only by the masked ROM version) Asynchronous event AEVH input H Asynchronous event AEVL input L Event input enable interrupt input IRQAEC 13.3 Register Descriptions The asynchronous event counter has the following registers. * * * * * * * Event counter PWM compare register (ECPWCR) Event counter PWM data register (ECPWDR) Input pin edge select register (AEGSR) Event counter control register (ECCR) Event counter control/status register (ECCSR) Event counter H (ECH) Event counter L (ECL) Rev. 1.00 Dec. 18, 2006 Page 279 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) 13.3.1 Event Counter PWM Compare Register (ECPWCR) ECPWCR sets the one conversion period of the event counter PWM waveform. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description One Conversion Period of Event Counter PWM Waveform When the ECPWME bit in AEGSR is 1, the event counter PWM is operating and therefore ECPWCR should not be modified. When changing the conversion period, the event counter PWM must be halted by clearing the ECPWME bit in AEGSR to 0 before modifying ECPWCR. ECPWCR15 1 ECPWCR14 1 ECPWCR13 1 ECPWCR12 1 ECPWCR11 1 ECPWCR10 1 ECPWCR9 ECPWCR8 ECPWCR7 ECPWCR6 ECPWCR5 ECPWCR4 ECPWCR3 ECPWCR2 ECPWCR1 ECPWCR0 1 1 1 1 1 1 1 1 1 1 Rev. 1.00 Dec. 18, 2006 Page 280 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) 13.3.2 Event Counter PWM Data Register (ECPWDR) ECPWDR controls data of the event counter PWM waveform generator. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name ECPWDR15 ECPWDR14 ECPWDR13 ECPWDR12 ECPWDR11 ECPWDR10 ECPWDR9 ECPWDR8 ECPWDR7 ECPWDR6 ECPWDR5 ECPWDR4 ECPWDR3 ECPWDR2 ECPWDR1 ECPWDR0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W W W W W W W W W W W W W W W W W Description Data Control of Event Counter PWM Waveform Generator When the ECPWME bit in AEGSR is 1, the event counter PWM is operating and therefore ECPWDR should not be modified. When changing the conversion cycle, the event counter PWM must be halted by clearing the ECPWME bit in AEGSR to 0 before modifying ECPWDR. Rev. 1.00 Dec. 18, 2006 Page 281 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) 13.3.3 Input Pin Edge Select Register (AEGSR) AEGSR selects rising, falling, or both edge sensing for the AEVH, AEVL, and IRQAEC pins. Bit 7 6 Bit Name AHEGS1 AHEGS0 Initial Value 0 0 R/W R/W R/W Description AEC Edge Select H Select rising, falling, or both edge sensing for the AEVH pin. 00: Falling edge on AEVH pin is sensed 01: Rising edge on AEVH pin is sensed 10: Both edges on AEVH pin are sensed 11: Setting prohibited 5 4 ALEGS1 ALEGS0 0 0 R/W R/W AEC Edge Select L Select rising, falling, or both edge sensing for the AEVL pin. 00: Falling edge on AEVL pin is sensed 01: Rising edge on AEVL pin is sensed 10: Both edges on AEVL pin are sensed 11: Setting prohibited 3 2 AIEGS1 AIEGS0 0 0 R/W R/W IRQAEC Edge Select Select rising, falling, or both edge sensing for the IRQAEC pin. 00: Falling edge on IRQAEC pin is sensed 01: Rising edge on IRQAEC pin is sensed 10: Both edges on IRQAEC pin are sensed 11: Setting prohibited 1 ECPWME 0 R/W Event Counter PWM Enable Controls operation of event counter PWM and selection of IRQAEC. 0: AEC PWM halted, IRQAEC selected 1: AEC PWM enabled, IRQAEC not selected 0 0 R/W Reserved This bit can be read from or written to. However, this bit should not be set to 1. Rev. 1.00 Dec. 18, 2006 Page 282 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) 13.3.4 Event Counter Control Register (ECCR) ECCR controls the counter input clock and IRQAEC/IECPWM. Bit 7 6 Bit Name ACKH1 ACKH0 Initial Value 0 0 R/W R/W R/W Description AEC Clock Select H Select the clock used by ECH. 00: AEVH pin input 01: /2 10: /4 11: /8 5 4 ACKL1 ACKL0 0 0 R/W R/W AEC Clock Select L Select the clock used by ECL. 00: AEVL pin input 01: /2 10: /4 11: /8 3 2 1 PWCK2 PWCK1 PWCK0 0 0 0 R/W R/W R/W Event Counter PWM Clock Select Select the event counter PWM clock. 000: /2 001: /4 010: /8 011: /16 1X0: /32 1X1 /64 0 0 R/W Reserved This bit can be read from or written to. However, this bit should not be set to 1. [Legend] X: Don't care. Rev. 1.00 Dec. 18, 2006 Page 283 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) 13.3.5 Event Counter Control/Status Register (ECCSR) ECCSR controls counter overflow detection, counter resetting, and count-up function. Bit 7 Bit Name OVH Initial Value 0 R/W R/W* Description Counter Overflow H This is a status flag indicating that ECH has overflowed. [Setting condition] When ECH overflows from H'FF to H'00 [Clearing condition] When this bit is written to 0 after reading OVH = 1 6 OVL 0 R/W* Counter Overflow L This is a status flag indicating that ECL has overflowed. [Setting condition] When ECL overflows from H'FF to H'00 while CH2 is set to 1 [Clearing condition] When this bit is written to 0 after reading OVL = 1 5 0 R/W Reserved Although this bit is readable/writable, it should not be set to 1. 4 CH2 0 R/W Channel Select Selects how ECH and ECL event counters are used 0: ECH and ECL are used together as a single-channel 16-bit event counter 1: ECH and ECL are used as two-channel 8-bit event counter 3 CUEH 0 R/W Count-Up Enable H Enables event clock input to ECH. 0: ECH event clock input is disabled (ECH value is retained) 1: ECH event clock input is enabled Rev. 1.00 Dec. 18, 2006 Page 284 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) Bit 2 Bit Name CUEL Initial Value 0 R/W R/W Description Count-Up Enable L Enables event clock input to ECL. 0: ECL event clock input is disabled (ECL value is retained) 1: ECL event clock input is enabled 1 CRCH 0 R/W Counter Reset Control H Controls resetting of ECH. 0: ECH is reset 1: ECH reset is cleared and count-up function is enabled 0 CRCL 0 R/W Counter Reset Control L Controls resetting of ECL. 0: ECL is reset 1: ECL reset is cleared and count-up function is enabled Note: * Only 0 can be written to clear the flag. Rev. 1.00 Dec. 18, 2006 Page 285 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) 13.3.6 Event Counter H (ECH) ECH is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECH also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL. Bit 7 6 5 4 3 2 1 0 Bit Name ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Either the external asynchronous event AEVH pin, /2, /4, or /8, or the overflow signal from lower 8-bit counter ECL can be selected as the input clock source. ECH can be cleared to H'00 by clearing the CRCH bit in ECCSR to 0. 13.3.7 Event Counter L (ECL) ECL is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECL also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECH. Bit 7 6 5 4 3 2 1 0 Bit Name ECL7 ECL6 ECL5 ECL4 ECL3 ECL2 ECL1 ECL0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Either the external asynchronous event AEVL pin, /2, /4, or /8 can be selected as the input clock source. ECL can be cleared to H'00 by clearing the CRCL bit in ECCSR to 0. Rev. 1.00 Dec. 18, 2006 Page 286 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) 13.4 13.4.1 Operation 16-Bit Counter Operation When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter. Any of four input clock sources--/2, /4, /8, or AEVL pin input--can be selected by means of bits ACKL1 and ACKL0 in ECCR. When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0. Note that the input clock is enabled when IRQAEC is high or IECPWM is high. When IRQAEC is low or IECPWM is low, the input clock is not input to the counter, which therefore does not operate. Figure 13.2 shows the software procedure when ECH and ECL are used as a 16-bit event counter. Start Clear CH2 to 0 Set ACKL1, ACKL0, ALEGS1, and ALEGS0 Clear CUEH, CUEL, CRCH, and CRCL to 0 Clear OVH and OVL to 0 Set CUEH, CUEL, CRCH, and CRCL to 1 End Figure 13.2 Software Procedure when Using ECH and ECL as 16-Bit Event Counter As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset, and as ACKL1 and ACKL0 are cleared to B'00, the operating clock is asynchronous event input from the AEVL pin (using falling edge sensing). When the next clock is input after the count value reaches H'FF in both ECH and ECL, ECH and ECL overflow from H'FFFF to H'0000, the OVH flag is set to 1 in ECCSR, the ECH and ECL count values each return to H'00, and counting up is restarted. When an overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU. Rev. 1.00 Dec. 18, 2006 Page 287 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) 13.4.2 8-Bit Counter Operation When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters. /2, /4, /8, or AEVH pin input can be selected as the input clock source for ECH by means of bits ACKH1 and ACKH0 in ECCR, and /2, /4, /8, or AEVL pin input can be selected as the input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR. Input sensing is selected with bits AHEGS1 and AHEGS0 when AEVH pin input is selected, and with bits ALEGS1 and ALEGS0 when AEVL pin input is selected. Note that the input clock is enabled when IRQAEC is high or IECPWM is high. When IRQAEC is low or IECPWM is low, the input clock is not input to the counter, which therefore does not operate. Figure 13.3 shows the software procedure when ECH and ECL are used as 8-bit event counters. Start Set CH2 to 1 Set ACKH1, ACKH0, ACKL1, ACKL0, AHEGS1, AHEGS0, ALEGS1, and ALEGS0 Clear CUEH, CUEL, CRCH, and CRCL to 0 Clear OVH and OVL to 0 Set CUEH, CUEL, CRCH, and CRCL to 1 End Figure 13.3 Software Procedure when Using ECH and ECL as 8-Bit Event Counters When the next clock is input after the ECH count value reaches H'FF, ECH overflows, the OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00, and counting up is restarted. Similarly, when the next clock is input after the ECL count value reaches H'FF, ECL overflows, the OVL flag is set to 1 in ECCSR, the ECL count value returns to H'00, and counting up is restarted. When an overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU. Rev. 1.00 Dec. 18, 2006 Page 288 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) 13.4.3 IRQAEC Operation When the ECPWME bit in AEGSR is 0, the ECH and ECL input clocks are enabled when IRQAEC goes high. When IRQAEC goes low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled from outside by controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually. IRQAEC can also operate as an interrupt source. Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated, IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an interrupt request is sent to the CPU. Rising, falling, or both edge sensing can be selected for the IRQAEC input pin with bits AIAGS1 and AIAGS0 in AEGSR. 13.4.4 Event Counter PWM Operation When the ECPWME bit in AEGSR is 1, the ECH and ECL input clocks are enabled when event counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled cyclically from outside by controlling event counter PWM. In this case, ECH and ECL cannot be controlled individually. IECPWM can also operate as an interrupt source. Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated, IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an interrupt request is sent to the CPU. Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits AIAGS1 and AIAGS0 in AEGSR. Figure 13.4 and table 13.2 show examples of event counter PWM operation. toff = (T x (Ndr +1)) - tcyc ton tcm = T x (Ncm +1) ton: toff: tcm: T: Ndr: Clock input enable time Clock input disable time One conversion period ECPWM input clock cycle Value of ECPWDR Fixed low when Ndr =H'FFFF Ncm: Value of ECPWCR tcyc: System clock () cycle time Figure 13.4 Event Counter Operation Waveform Rev. 1.00 Dec. 18, 2006 Page 289 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) Note: Ndr and Ncm above must be set so that Ndr < Ncm. If the settings do not satisfy this condition, the output of the event counter PWM is fixed low. Table 13.2 Examples of Event Counter PWM Operation Conditions: fosc = 4 MHz, f = 4 MHz, high-speed active mode, ECPWCR value (Ncm) = H'7A11, ECPWDR value (Ndr) = H'16E3 Clock Source Selection /2 /4 /8 /16 /32 /64 Note: * Clock Source ECPWCR ECPWDR Cycle (T)* Value (Ncm) Value (Ndr) 0.5 s 1 s 2 s 4 s 8 s 16 s toff minimum width H'7A11 D'31249 H'16E3 D'5859 toff = (T x (Ndr + 1)) - tcyc 2.92975 ms 5.85975 ms 11.71975 ms 23.43975 ms 46.87975 ms 93.75975 ms tcm = T x (Ncm + 1) 15.625 ms 31.25 ms 62.5 ms 125.0 ms 250.0 ms 500.0 ms ton = tcm - toff 12.69525 ms 25.39025 ms 50.78025 ms 101.56025 ms 203.12025 ms 406.24025 ms 13.4.5 Operation of Clock Input Enable/Disable Function The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in AEGSR is 0, and by the event counter PWM output, IECPWM when ECPWME in AEGSR is 1. As this function forcibly terminates the clock input by each signal, a maximum error of one count will occur depending on the IRQAEC or IECPWM timing. Figure 13.5 shows an example of the operation. Input event IRQAEC or IECPWM Edge generated by clock return Actually counted clock source Counter value N N+1 N+2 N+3 N+4 N+5 N+6 Clock stopped Figure 13.5 Example of Clock Control Operation Rev. 1.00 Dec. 18, 2006 Page 290 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) 13.5 Operating States of Asynchronous Event Counter The operating states of the asynchronous event counter are shown in table 13.3. Table 13.3 Operating States of Asynchronous Event Counter Operating Mode AEGSR ECCR ECCSR ECH ECL IRQAEC Reset Reset Reset Reset Reset Reset Reset Active Functions Functions Functions Functions Functions Functions Functions Sleep Functions Functions Functions Functions Functions Functions Functions Watch Retained*1 Retained* Retained* 1 Sub-active Sub-sleep Standby Functions Functions Functions Functions*2 Functions Functions Retained 2 Module Standby Retained Retained Retained Halted Halted Retained*4 Retained Functions Functions Functions Functions*2 Functions* Functions Retained 2 Retained*1 Retained* Retained* 1 1 1 Functions*1*2 Functions* * Retained* Retained 3 12 Functions*1*2 Functions* * Retained* Retained 3 12 Event counter Reset PWM Notes: 1. When an asynchronous external event is input, the counter increments. The interrupt request is raised when an overflow has occurred. 2. Functions when asynchronous external events are selected; halted and retained otherwise. 3. Clock control by IRQAEC operates, but interrupts do not. 4. As the clock is stopped in module standby mode, IRQAEC has no effect. Rev. 1.00 Dec. 18, 2006 Page 291 of 568 REJ09B0348-0100 Section 13 Asynchronous Event Counter (AEC) 13.6 Usage Notes 1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR in 8-bit mode and clear bit CUEL to 0 in 16-bit mode to prevent asynchronous event input to the counter. The correct value will not be returned if the event counter increments while being read. 2. For input to the AEVH and AEVL pins, use a clock with a frequency of up to 4.2 MHz within the range from 1.8 to 3.6 V and up to 10 MHz within the range from 2.7 to 3.6 V. For the high and low widths of the clock, see section 23, Electrical Characteristics. The duty cycle is arbitrary. Table 13.4 shows a maximum clock frequency. Table 13.4 Maximum Clock Frequency Mode Active (high-speed), sleep (high-speed) Active (medium-speed), sleep (medium-speed) (OSC/8) (OSC/16) (OSC/32) fOSC = 1 MHz to 4 MHz Watch, subactive, subsleep, standby W = 32.768 kHz or 38.4 kHz (OSC/64) (W/2) (W/4) (W/8) Maximum Clock Frequency Input to AEVH/AEVL Pin 10 MHz 2 * fOSC fOSC 1/2 * fOSC 1/4 * fOSC 1000 kHz 500 kHz 250 kHz 3. When AEC uses with 16-bit mode, set CUEH in ECCSR to 1 first, set CRCH in ECCSR to 1 second, or set both CUEH and CRCH to 1 at same time before clock input. When AEC is operating on 16-bit mode, do not change CUEH. Otherwise, ECH will be miscounted up. 4. When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWCR and ECPWDR should not be modified. When changing the data, clear the ECPWME bit in AEGSR to 0 (halt the event counter PWM) before modifying these registers. 5. The event counter PWM data register and event counter PWM compare register must be set so that event counter PWM data register < event counter PWM compare register. If the settings do not satisfy this condition, do not set ECPWME to 1 in AEGSR. 6. As synchronization is established internally when an IRQAEC interrupt is generated, a maximum error of 1 tcyc will occur between clock halting and interrupt acceptance. Rev. 1.00 Dec. 18, 2006 Page 292 of 568 REJ09B0348-0100 Section 14 Watchdog Timer Section 14 Watchdog Timer This LSI incorporates the watchdog timer (WDT). The WDT is an 8-bit timer that can generate an internal reset signal if a system becomes uncontrolled and prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog timer function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. 14.1 Features The WDT features are described below. * Selectable from nine counter input clocks Eight internal clock sources (/64, /128, /256, /512, /1024, /2048, /4096, and /8192) or the on-chip oscillator (ROSC/2048) can be selected as the timer-counter clock. * Watchdog timer mode If the counter overflows, this LSI is internally reset. * Interval timer mode If the counter overflows, an interval timer interrupt is generated. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 6.4, Module Standby Function.) Figure 14.1 shows a block diagram of the WDT. Rev. 1.00 Dec. 18, 2006 Page 293 of 568 REJ09B0348-0100 Section 14 Watchdog Timer TMWD on-chip oscillator CLK PSS TCWD TCSRWD2 [Legend] TCSRWD1: TCSRWD2: TCWD: TMWD: PSS: Timer control/status register WD Timer control/status register WD2 Timer counter WD Timer mode register WD Prescaler S Interrupt/reset control Internal reset signal or interrupt request signal Figure 14.1 Block Diagram of Watchdog Timer 14.2 Register Descriptions The watchdog timer has the following registers. * * * * Timer control/status register WD1 (TCSRWD1) Timer control/status register WD2 (TCSRWD2) Timer counter WD (TCWD) Timer mode register WD (TMWD) Rev. 1.00 Dec. 18, 2006 Page 294 of 568 REJ09B0348-0100 Internal data bus TCSRWD1 Section 14 Watchdog Timer 14.2.1 Timer Control/Status Register WD1 (TCSRWD1) TCSRWD1 performs the TCSRWD1 and TCWD write control. TCSRWD1 also controls the watchdog timer operation and indicates the operating state. TCSRWD1 must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value. Bit 7 Bit Name B6WI Initial Value 1 R/W R/W Description Bit 6 Write Inhibit The TCWE bit can be written only when the write value of the B6WI bit is 0. This bit is always read as 1. 6 TCWE 0 R/W Timer Counter WD Write Enable TCWD can be written when the TCWE bit is set to 1. When writing data to this bit, the write value for bit 7 must be 0. 5 B4WI 1 R/W Bit 4 Write Inhibit The TCSRWE bit can be written only when the write value of the B4WI bit is 0. This bit is always read as 1. 4 TCSRWE 0 R/W Timer Control/Status Register WD Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1. When writing data to this bit, the write value for bit 5 must be 0. 3 B2WI 1 R/W Bit 2 Write Inhibit The WDON bit can be written only when the write value of the B2WI bit is 0. This bit is always read as 1. Rev. 1.00 Dec. 18, 2006 Page 295 of 568 REJ09B0348-0100 Section 14 Watchdog Timer Bit 2 Bit Name WDON Initial Value 0 R/W R/W Description Watchdog Timer On* TCWD starts counting up when the WDON bit is set to 1 and halts when the WDON bit is cleared to 0. [Setting condition] When 1 is written to the WDON bit and 0 to the B2WI bit while the TCSRWE bit is 1 [Clearing conditions] * * Reset by RES pin When 0 is written to the WDON bit and 0 to the B2WI bit while the TCSRWE bit is 1 1 B0WI 1 R/W Bit 0 Write Inhibit The WRST bit can be written only when the write value of the B0WI bit is 0. This bit is always read as 1. 0 WRST 0 R/W Watchdog Timer Reset [Setting condition] When TCWD overflows and an internal reset signal is generated [Clearing conditions] * * Reset by RES pin When 0 is written to the WRST bit and 0 to the B0WI bit while the TCSRWE bit is 1 Note: When main internal clock signal has been selected by the timer mode register (TMWD) (i.e., CKS3 is set to 1) and watch mode or standby mode is entered, be sure to clear the WDON bit to 0 to stop the counting of the timer counter WD (TCWD). Rev. 1.00 Dec. 18, 2006 Page 296 of 568 REJ09B0348-0100 Section 14 Watchdog Timer 14.2.2 Timer Control/Status Register WD2 (TCSRWD2) TCSRWD2 performs the TCSRWD2 write control, mode switching, and interrupt control. TCSRWD2 must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value. Bit 7 Bit Name OVF Initial Value 0 R/W 1 Description 6 B5WI 1 5 WT/IT 0 4 B3WI 1 3 IEOVF 0 R/(W)* Overflow Flag Indicates that TCWD has overflowed (changes from H'FF to H'00). [Setting condition] When TCWD overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, this bit is cleared automatically by the internal reset after it has been set. [Clearing condition] * When TCSRWD2 is read when OVF = 1, then 0 is 4 written to OVF* 2 R/(W)* Bit 5 Write Inhibit The WT/IT bit can be written only when the write value of the B5WI bit is 0. This bit is always read as 1. 3 R/(W)* Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Watchdog timer mode 1: Interval timer mode R/(W)*2 Bit 3 Write Inhibit The IEOVF bit can be written only when the write value of the B3WI bit is 0. This bit is always read as 1. R/(W)*3 Overflow Interrupt Enable Enables or disables an overflow interrupt request in interval timer mode. 0: Disables an overflow interrupt 1: Enables an overflow interrupt Rev. 1.00 Dec. 18, 2006 Page 297 of 568 REJ09B0348-0100 Section 14 Watchdog Timer Bit 2 to 0 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1. Notes: 1. Only 0 can be written to clear the flag. 2. Write operation is necessary because this bit controls data writing to other bit. This bit is always read as 1. 3. Writing is possible only when the write conditions are satisfied. 4. In subactive mode, clear this flag after setting the CKS3 to CKS0 bits in TMWD to B'0XXX (on-chip oscillator). Rev. 1.00 Dec. 18, 2006 Page 298 of 568 REJ09B0348-0100 Section 14 Watchdog Timer 14.2.3 Timer Counter WD (TCWD) TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated in watchdog timer mode, the WRST bit in TCSRWD1 is set to 1, and the OVF bit in TCSRWD2 is set to 1. TCWD is initialized to H'00. 14.2.4 Timer Mode Register WD (TMWD) TMWD selects the input clock. Bit 7 to 4 3 2 1 0 Bit Name CKS3 CKS2 CKS1 CKS0 Initial Value All 1 1 1 1 1 R/W R/W R/W R/W R/W Description Reserved These bits are always read as 1. Clock Select 3 to 0 Select the clock to be input to TCWD. 1000: Internal clock: counts on /64 1001: Internal clock: counts on /128 1010: Internal clock: counts on /256 1011: Internal clock: counts on /512 1100: Internal clock: counts on /1024 1101: Internal clock: counts on /2048 1110: Internal clock: counts on /4096 1111: Internal clock: counts on /8192 0XXX: on-chip oscillator: counts on ROSC/2048 For the on-chip oscillator overflow periods, see section 23, Electrical Characteristics. In active (medium-speed) mode or sleep (mediumspeed) mode, the setting of B'0XXX and interval timer mode is disabled. [Legend] X: Don't care. Rev. 1.00 Dec. 18, 2006 Page 299 of 568 REJ09B0348-0100 Section 14 Watchdog Timer 14.3 14.3.1 Operation Watchdog Timer Mode The watchdog timer is provided with an 8-bit up-counter. To use it as the watchdog timer, clear the WT/IT bit in TCSRWD2 to 0. (To write the WT/IT bit, two write accesses are required.) If 1 is written to the WDON bit and 0 to the B2WI bit simultaneously when the TCSRWE bit in TCSRWD1 is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD1 are required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 512 osc clock cycles. TCWD is a writable counter, and when a value is set in TCWD, the count-up starts from that value. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value. Figure 14.2 shows an example of watchdog timer operation. Example: With 30-ms overflow period when = 4 MHz 4 x 106 8192 x 30 x 10-3 = 14.6 Therefore, 256 - 15 = 241 (H'F1) is set in TCW. H'FF H'F1 TCWD count value TCWD overflow H'00 Start H'F1 written to TCWD H'F1 written to TCWD Reset generated Internal reset signal 512 osc clock cycles Figure 14.2 Example of Watchdog Timer Operation Rev. 1.00 Dec. 18, 2006 Page 300 of 568 REJ09B0348-0100 Section 14 Watchdog Timer 14.3.2 Interval Timer Mode Figure 14.3 shows the operation in interval timer mode. To use the WDT as an interval timer, set the WT/IT bit in TCSRWD2 to 1. When the WDT is used as an interval timer, an interval timer interrupt request is generated each time the TCNT overflows. Therefore, an interval timer interrupt can be generated at intervals. H'FF TCNT count value Time H'00 WT/IT = 0 TME = 1 Interval timer Interval timer Interval timer Interval timer Interval timer interrupt interrupt interrupt interrupt interrupt request generated request generated request generated request generated request generated Figure 14.3 Interval Timer Mode Operation 14.3.3 Timing of Overflow Flag (OVF) Setting Figure 14.4 shows the timing of the OVF flag setting. The OVF flag in TCSRWD2 is set to 1 if TCNT overflows. At the same time, a reset signal is output in watchdog timer mode and an interval timer interrupt is generated in interval timer mode. TCNT H'FF H'00 Overflow signal OVF Figure 14.4 Timing of OVF Flag Setting Rev. 1.00 Dec. 18, 2006 Page 301 of 568 REJ09B0348-0100 Section 14 Watchdog Timer 14.4 Interrupt During interval timer mode operation, an overflow generates an interval timer interrupt. The interval timer interrupt is requested whenever the OVF flag is set to 1 while the IEOVF bit in TCSRWD2 is set to 1. The OVF flag must be cleared to 0 in the interrupt handling routine. 14.5 14.5.1 Usage Notes Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched between watchdog timer and interval timer, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the WDON bit to 0) before switching the mode. 14.5.2 Module Standby Mode Control The WDCKSTP bit in CKSTPR2 is valid when the WDON bit in the timer control/status register 1 (TCSRWD1) is cleared to 0. The WDCKSTP bit can be cleared to 0 while the WDON bit is set to 1 (while the watchdog timer is operating). However, the watchdog timer does not enter module standby mode but continues operating. When the WDON bit is cleared to 0 by software after the watchdog timer stops operating, the WDCKSTP bit is valid at the same time and the watchdog timer enters module standby mode. 14.5.3 Clearing of WT/IT and IEOVF Bits in TCSRWD2 When clearing the WT/IT and IEOVF bits in the timer control/status register WD2 (TCSRWD2), follow the procedure given in assembly language in figure 14.5, or writing may be unsuccessful due to dependence on the address of the clear instruction. Success or failure of writing depends on the two lower-order bits of the address of the transfer instruction used to write to TCSRWD2. For this reason, ensure that the assembly segment given in figure 14.5 is allocated with the same address offsets as in the figure. Rev. 1.00 Dec. 18, 2006 Page 302 of 568 REJ09B0348-0100 Section 14 Watchdog Timer Address Offset +H'0000 +H'0002 +H'0004 +H'0006 +H'0008 +H'000C +H'000E MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B NOP Assembly Listing #xx, Rn Rn, @TCSRWD2: 8 @TCSRWD2: 8, Rm #yy, Rm LABEL: 16 Rn, @TCSRWD2: 8 ; ; Clear (first round) ; Read from TCSRWD2 ; Check if clearing was successful. ; If successful, jump to LABEL. ; Clear (second round) LABEL: Bit to be Cleared Simultaneous clearing of bits WT/IT and IEOVF Clear bit WT/IT only Clear bit IEOVF only xx Value in First Line H'87 H'97 H'C7 yy Value in Fourth Line H'28 H'20 H'08 Notes: * Set TCSRWD2 to an absolute 8-bit address, and the target address for branching by the BEQ instruction to an absolute 16-bit address. * Use two 8-bit general registers as Rn and Rm. * Do not modify or add any instructions, or change the order of these instructions. Since modification may take place unexpectedly according to the settings of the compiler and linker, be sure to confirm the address offsets. Figure 14.5 How to Clear WT/IT and IEOVF Bits in TCSRWD2 to 0 Rev. 1.00 Dec. 18, 2006 Page 303 of 568 REJ09B0348-0100 Section 14 Watchdog Timer Rev. 1.00 Dec. 18, 2006 Page 304 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Section 15 Serial Communication Interface 3 (SCI3, IrDA) The serial communication interface 3 (SCI3) can handle both asynchronous and clock synchronous serial communication. In the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). Table 15.1 shows the SCI3 channel configuration. The SCI3_1 can transmit and receive IrDA communication waveforms based on the Infrared Data Association (IrDA) standard version 1.0. 15.1 Features * Choice of asynchronous or clock synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected * On-chip baud rate generator, internal clock, or external clock can be selected as a transfer clock source. * Six interrupt sources Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity error. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 6.4, Module Standby Function.) Asynchronous mode Data length: 7, 8, or 5 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RXD32 pin level directly in the case of a framing error Note: When using serial communication interface 3 in the masked ROM version, do not use the on-chip oscillator. Rev. 1.00 Dec. 18, 2006 Page 305 of 568 REJ09B0348-0100 * * * * * Section 15 Serial Communication Interface 3 (SCI3, IrDA) Clock synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors detected Table 15.1 SCI3 Channel Configuration Channel Channel 1 Abbreviation SCI3_1 Pin*1 SCK31 RXD31 TXD31 Register*2 SMR3_1 BRR3_1 SCR3_1 TDR3_1 SSR3_1 RDR3_1 RSR3_1 TSR3_1 IrCR Channel 2 SCI3_2 SCK32 RXD32 TXD32 SMR3_2 BRR3_2 SCR3_2 TDR3_2 SSR3_2 RDR3_2 RSR3_2 TSR3_2 Register Address H'FF98 H'FF99 H'FF9A H'FF9B H'FF9C H'FF9D H'FFA7 H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFAD Notes: 1. Pin names SCK3, RXD3, and TXD3 are used in the text for all channels, omitting the channel designation. 2. In the text, channel description is omitted for registers and bits. Rev. 1.00 Dec. 18, 2006 Page 306 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Figure 15.1 (1) shows a block diagram of the SCI3_1 and figure 15.1 (2) shows that of the SCI3_2. SCK31 External clock Baud rate generator Internal clock (/64, /16, w/2, ) BRC3_1 Clock BRR3_1 Transmit/receive control circuit SCR3_1 SSR3_1 TSR3_1 TDR3_1 RSR3_1 RDR3_1 TXD31 RXD31 SPCR IrCR Interrupt request (TEI31, TXI31, RXI31, ERI31) [Legend] RSR3_1: Receive shift register 3_1 RDR3_1:Receive data register 3_1 TSR3_1: Transmit shift register 3_1 TDR3_1: Transmit data register 3_1 SMR3_1:Serial mode register 3_1 SCR3_1: Serial control register 3_1 SSR3_1: Serial status register 3_1 BRR3_1: Bit rate register 3_1 BRC3_1: Bit rate counter 3_1 SPCR: Serial port control register IrDA control register IrCR: Figure 15.1 (1) Block Diagram of SCI3_1 Rev. 1.00 Dec. 18, 2006 Page 307 of 568 REJ09B0348-0100 Internal data bus SMR3_1 Section 15 Serial Communication Interface 3 (SCI3, IrDA) SCK32 External clock Baud rate generator Internal clock (/64, /16, w/2, ) BRC3_2 Clock BRR3_2 Transmit/receive control circuit SCR3_2 SSR3_2 TXD32 TSR3_2 TDR3_2 RXD32 SPCR RSR3_2 RDR3_2 Interrupt request (TEI32, TXI32, RXI32, ERI32) [Legend] RSR3_2: RDR3_2: TSR3_2: TDR3_2: SMR3_2: SCR3_2: SSR3_2: BRR3_2: BRC3_2: SPCR: Receive shift register 3_2 Receive data register 3_2 Transmit shift register 3_2 Transmit data register 3_2 Serial mode register 3_2 Serial control register 3_2 Serial status register 3_2 Bit rate register 3_2 Bit rate counter 3_2 Serial port control register Figure 15.1 (2) Block Diagram of SCI3_2 Rev. 1.00 Dec. 18, 2006 Page 308 of 568 REJ09B0348-0100 Internal data bus SMR3_2 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.2 Input/Output Pins Table 15.2 shows the SCI3 pin configuration. Table 15.2 Pin Configuration Pin Name SCI3 clock SCI3 receive data input SCI3 transmit data output Abbreviation I/O SCK31, SCK32 RXD31, RXD32 TXD31, TXD32 I/O Input Output Function SCI3 clock input/output SCI3 receive data input SCI3 transmit data output 15.3 Register Descriptions The SCI3 has the following registers for each channel. * * * * * * * * * * Receive shift register 3 (RSR3)* Receive data register 3 (RDR3)* Transmit shift register 3 (TSR3)* Transmit data register 3 (TDR3)* Serial mode register 3 (SMR3)* Serial control register 3 (SCR3)* Serial status register 3 (SSR3)* Bit rate register 3 (BRR3)* Serial port control register (SPCR) IrDA control register (IrCR) Note: * These register names are abbreviated to RSR, RDR, TSR, TDR, SMR, SCR, SSR, and BRR in the text. Rev. 1.00 Dec. 18, 2006 Page 309 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.3.1 Receive Shift Register (RSR) RSR is a shift register that receives serial data input from the RXD31 or RXD32 pin and converts it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 15.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI3 has received one byte of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. RDR is initialized to H'00. RDR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode. 15.3.3 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first transfers transmit data from TDR to TSR automatically, then sends the data that starts from the LSB to the TXD31 or TXD32 pin. Data transfer from TDR to TSR is not performed if no data has been written to TDR (if the TDRE bit in SSR is set to 1). TSR cannot be directly accessed by the CPU. 15.3.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during transmission of one-frame data, the SCI3 transfers the written data to TSR to continue transmission. To achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF. TDR is initialized to H'FF by a reset or in standby mode, watch mode, or module standby mode. Rev. 1.00 Dec. 18, 2006 Page 310 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.3.5 Serial Mode Register (SMR) SMR sets the SCI3's serial communication format and selects the clock source for the on-chip baud rate generator. SMR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode. Bit 7 Bit Name COM Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clock synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 or 5 bits as the data length. 1: Selects 7 or 5 bits as the data length. When 7-bit data is selected. the MSB (bit 7) in TDR is not transmitted. To select 5 bits as the data length, set 1 to both the PE and MP bits. The three most significant bits (bits 7, 6, and 5) in TDR are not transmitted. In clock synchronous mode, the data length is fixed to 8 bits regardless of the CHR bit setting. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. In clock synchronous mode, parity bit addition and checking is not performed regardless of the PE bit setting. Rev. 1.00 Dec. 18, 2006 Page 311 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Bit 4 Bit Name PM Initial Value 0 R/W R/W Description Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. When even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number, in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. When odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number, in reception, a check is carried out to confirm that the number of 1bits in the receive data plus the parity bit is an odd number. If parity bit addition and checking is disabled in clock synchronous mode and asynchronous mode, the PM bit setting is invalid. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits For reception, only the first stop bit is checked, regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 MP 0 R/W Five-Bit Communications When this bit is set to 1, formatting in 5-bit communications is enabled. When setting this bit to 1, be sure to set the PE bit (bit 5 of this register) simultaneously to 1. Rev. 1.00 Dec. 18, 2006 Page 312 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Bit 1 0 Bit Name CKS1 CKS0 Initial Value 0 0 R/W R/W R/W Description Clock Select 0 and 1 These bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: w/2 or w clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) When the setting value is 0 in active (mediumspeed/high-speed) mode and sleep (mediumspeed/high-speed) mode w/2 clock is set. In subacive mode and subsleep mode, w clock is set. The SCI3 is enabled only, when w/2 is selected for the CPU operating clock. For the relationship between the bit rate register setting and the baud rate, see section 15.3.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 15.3.8, Bit Rate Register (BRR)). Rev. 1.00 Dec. 18, 2006 Page 313 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.3.6 Serial Control Register (SCR) SCR enables or disables SCI3 transfer operations and interrupt requests, and selects the transfer clock source. For details on interrupt requests, refer to section 15.7, Interrupt Requests. SCR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode. Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, the TXI (TXI32) interrupt request is enabled. TXI (TXI32) can be released by clearing the TDRE it or TI bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI (RXI32) and ERI (ERI32) can be released by clearing the RDRF bit or the FER, PER, or OER error flag to 0, or by clearing the RIE bit to 0. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. When this bit is 0, the TDRE bit in SSR is fixed at 1. When transmit data is written to TDR while this bit is 1, Bit TDRE in SSR is cleared to 0 and serial data tansmission is started. Be sure to carry out SMR settings, and setting of bit SPC31 or SPC32 in SPCR, to decide the transmission format before setting bit TE to 1. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. In this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in clock synchronous mode. Be sure to carry out the SMR settings to decide the reception format before setting bit RE to 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is cleared to 0, and retain their previous state Rev. 1.00 Dec. 18, 2006 Page 314 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Bit 3 2 Bit Name MPIE TEIE Initial Value 0 0 R/W R/W R/W Description Reserved Transmit End Interrupt Enable When this bit is set to 1, the TEI interrupt request is enabled. TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by clearing bit TEIE to 0. 1 0 CKE1 CKE0 0 0 R/W R/W Clock Enable 0 and 1 Select the clock source. Asynchronous mode: 00: Internal baud rate generator (SCK31 or SCK32 pin functions as an I/O port) 01: Internal baud rate generator (Outputs a clock of the same frequency as the bit rate from the SCK31 or SCK32 pin) 10: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK31 or SCK32 pin) 11: Reserved Clock synchronous mode: 00: Internal clock (SCK31 or SCK32 pin functions as clock output) 01: Reserved 10: External clock (SCK31 or SCK32 pin functions as clock input) 11: Reserved Rev. 1.00 Dec. 18, 2006 Page 315 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.3.7 Serial Status Register (SSR) SSR consists of status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. SSR is initialized to H'84 by a reset or in standby mode, watch mode, or module standby mode. Bit 7 Bit Name TDRE Initial Value 1 R/W Description R/(W)* Transmit Data Register Empty Indicates that transmit data is stored in TDR. [Setting conditions] * * * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1 When the transmit data is written to TDR [Clearing conditions] 6 RDRF 0 R/(W)* Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 [Clearing conditions] * When data is read from RDR If an error is detected in reception, or if the RE bit in SCR has been cleared to 0, RDR and bit RDRF are not affected and retain their previous state. Note that if data reception is completed while bit RDRF is still set to 1, an overrun error (OER) will occur and the receive data will be lost. Rev. 1.00 Dec. 18, 2006 Page 316 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Bit 5 Bit Name OER Initial Value 0 R/W Description R/(W)* Overrun Error [Setting condition] * * When an overrun error occurs in reception When 0 is written to OER after reading OER = 1 [Clearing condition] When bit RE in SCR is cleared to 0, bit OER is not affected and retains its previous state. When an overrun error occurs, RDR retains the receive data it held before the overrun error occurred, and data received after the error is lost. Reception cannot be continued with bit OER set to 1, and in clock synchronous mode, transmission cannot be continued either. 4 FER 0 R/(W)* Framing Error [Setting condition] * * When a framing error occurs in reception When 0 is written to FER after reading FER = 1 [Clearing condition] When bit RE in SCR is cleared to 0, bit FER is not affected and retains its previous state. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. When a framing error occurs, the receive data is transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER set to 1. In clock synchronous mode, neither transmission nor reception is possible when bit FER is set to 1. Rev. 1.00 Dec. 18, 2006 Page 317 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Bit 3 Bit Name PER Initial Value 0 R/W Description R/(W)* Parity Error [Setting condition] * * When a parity error is generated during reception When 0 is written to PER after reading PER = 1 [Clearing condition] When bit RE in SCR is cleared to 0, bit PER is not affected and retains its previous state. * Receive data in which a parity error has occurred is still transferred to RDR, but bit RDRF is not set. Reception cannot be continued with bit PER set to 1. In clock synchronous mode, neither transmission nor reception is possible when bit PER is set to 1. 2 TEND 1 R Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character When 0 is written to TDRE after readingTDRE = 1 When the transmit data is written to TDR [Clearing conditions] * * 1 0 Note: * MPBR MPBT 0 0 R R/W Reserved This is a read-only bit and cannot be modified. Reserved Only 0 should be written to this bit. Only 0 can be written to clear the flag. Rev. 1.00 Dec. 18, 2006 Page 318 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.3.8 Bit Rate Register (BRR) BRR is an 8-bit readable/writable register that adjusts the bit rate. BRR is initialized to H'FF. Table 15.3 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 in SMR in asynchronous mode. Table 15.5 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 15.3 and 15.5 are values in active (high-speed) mode. Table 15.6 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 in SMR in clock synchronous mode. The values shown in table 15.6 are values in active (high-speed) mode. The N setting in BRR and error for other operating frequencies and bit rates can be obtained by the following formulas: [Asynchronous Mode] In active (medium/high speed) or sleep (medium-speed/high-speed) mode: N= OSC -1 32 x 22n x B In subactive or subsleep mode: N= OSC -1 64 x 22n x B B (bit rate obtained from n, N, ) - R (bit rate in left-hand column in table 15.3) R (bit rate in left-hand column in table 15.3) Error (%) = x 100 [Legend] B: N: OSC: n: Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Value of OSC (Hz) Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 15.4) Rev. 1.00 Dec. 18, 2006 Page 319 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 32.8kHz n -- -- -- 0 -- -- -- -- -- -- -- -- -- N -- -- -- 1 -- -- -- -- -- -- -- -- -- Error (%) -- -- -- 2.50 -- -- -- -- -- -- -- -- -- n -- 0 0 -- 0 0 -- -- -- -- -- -- -- 38.4kHz N -- 3 2 -- 1 0 -- -- -- -- -- -- -- Error (%) -- 0.00 0.00 -- 0.00 0.00 0.00 -- -- -- -- -- -- n 2 2 2 0 0 0 0 0 0 -- -- 0 -- 2MHz N 35 25 19 249 207 103 51 25 12 -- -- 1 -- Error (%) -1.36 0.16 -2.34 0.00 0.16 0.16 0.16 0.16 0.16 -- -- 0.00 -- n 2 2 3 3 0 0 0 0 0 0 -- -- -- 2.097152MHz N 36 26 4 3 217 108 54 26 13 6 -- -- -- Error (%) 0.64 1.14 2.40 2.40 0.21 0.21 -0.70 1.14 -2.48 -2.48 -- -- -- Rev. 1.00 Dec. 18, 2006 Page 320 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 2.4576MHz n 3 3 3 2 3 3 3 2 2 0 0 -- 0 N 10 7 5 18 3 1 0 1 0 7 3 -- 1 Error (%) -0.83 0.00 0.00 1.05 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 2 2 2 3 0 0 0 0 0 0 0 -- 3MHz N 52 38 28 22 4 155 77 38 19 9 4 2 -- Error (%) 0.50 0.16 1.02 1.90 2.34 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- n 2 3 3 2 3 3 2 2 0 0 0 -- 0 3.6864MHz N 64 11 8 28 5 2 5 2 23 11 5 -- 2 Error (%) 0.70 0.00 0.00 -0.69 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 2 2 2 2 0 0 0 0 0 -- 0 -- 4MHz N 70 51 38 30 25 207 103 51 25 12 -- 3 -- Error (%) 0.03 0.16 0.16 0.81 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 -- Rev. 1.00 Dec. 18, 2006 Page 321 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 4.9152MHz n 2 3 3 2 3 3 3 3 2 2 0 0 0 N 86 15 11 37 7 3 1 0 1 0 7 4 3 Error (%) 0.31 0.00 0.00 1.05 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 2 2 0 0 0 0 2 0 0 0 5MHz N 88 64 48 38 32 252 129 64 32 0 7 4 3 Error (%) -0.25 0.16 -0.35 0.16 -1.36 1.73 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 n 2 2 2 2 2 3 0 0 0 0 0 0 0 6MHz N 106 77 58 46 38 4 155 77 38 19 9 5 4 Error (%) -0.44 0.16 -0.69 -0.27 0.16 -2.34 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 n 2 3 3 3 3 3 2 2 0 0 0 0 0 6.144MHz N 108 19 14 11 9 4 9 4 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.4 0.00 Rev. 1.00 Dec. 18, 2006 Page 322 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (4) Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 7.3728MHz n 2 3 3 2 3 3 3 2 2 0 0 -- 0 N 130 23 17 57 11 5 2 5 2 23 11 -- 5 Error (%) -0.07 0.00 0.00 -0.69 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 2 2 2 2 2 2 0 0 0 0 0 -- 8MHz N 141 103 77 62 51 25 12 103 51 25 12 7 -- Error (%) 0.03 0.16 0.16 -0.79 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -- n 2 3 3 2 3 3 3 3 3 2 2 0 0 9.8304MHz N 174 31 23 76 15 7 3 1 0 1 0 9 7 Error (%) -0.26 0.00 0.00 -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 2 2 2 2 0 0 0 0 0 0 10MHz N 177 129 97 77 64 32 15 129 64 32 15 9 7 Error (%) -0.25 0.16 -0.35 0.16 0.16 -1.36 1.73 0.16 0.16 -1.36 1.73 0.00 1.73 Table 15.4 Relation between n and Clock SMR Setting n 0 0 2 3 Clock W/2* /W* 1 2 CKS1 0 0 1 1 CKS0 0 1 0 1 /16 /64 Notes: 1. W/2 clock in active (medium-speed/high-speed) mode and sleep (medium-speed/highspeed) mode 2. W clock in subactive mode and subsleep mode In subactive or subsleep mode, the SCI3 can be operated only when CPU clock is W/2. Rev. 1.00 Dec. 18, 2006 Page 323 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Table 15.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Setting (MHz) 0.0328* 0.0384* 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 Note: * Maximum Bit Rate (bit/s) 512.5 600 62500 65535 76800 93750 115200 125000 153595 156250 187500 192000 230400 250000 307200 312500 When CKS1 = 0 and CKS0 = 1 in SMR n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev. 1.00 Dec. 18, 2006 Page 324 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Table 15.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (1) Bit Rate (bit/s) 200 250 300 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M Note: * n 0 0 0 0 0 32.8 kHz N 20 15 13 75 3 Error (%) -2.38 2.50 -2.38 2.50 2.50 n 0 0 0 N 23 18 15 38.4 kHz Error (%) 0.00 1.05 0.00 n 2 2 2 2 2 0 0 0 0 0 0 0 0* N 155 124 103 62 30 199 99 49 19 9 4 1 0* 2 MHz Error (%) 0.16 0.00 0.16 -0.79 0.81 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00* Continuous transmission/reception is not possible. Rev. 1.00 Dec. 18, 2006 Page 325 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Table 15.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (2) Bit Rate (bit/s) 200 250 300 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M Note: * n 3 2 2 2 2 2 0 0 0 0 0 0 0 0* N 77 249 207 124 62 24 199 99 39 19 9 3 1 0* 4 MHz Error (%) 0.16 0.00 0.16 0.00 -0.79 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00* n 3 3 3 2 2 2 2 0 0 0 0 0 0 0 N 155 124 103 249 124 49 24 199 79 39 19 7 3 1 8 MHz Error (%) 0.16 0.00 0.16 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 3 3 3 3 2 2 2 2 0 0 0 0 0 N 194 155 129 77 155 62 30 15 99 49 24 9 4 10 MHz Error (%) 0.16 0.16 0.16 0.16 0.16 -0.79 0.81 -2.34 0.00 0.00 0.00 0.00 0.00 Continuous transmission/reception is not possible. The value set in BRR is given by the following formula: In active (medium- or high-speed) or sleep (medium- or high-speed) mode: OSC -1 N= 4 x 22n x B In subactive or subsleep mode: OSC N= -1 8 x 22n x B B: N: OSC: n: Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Value of OSC (Hz) Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 15.7.) Rev. 1.00 Dec. 18, 2006 Page 326 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Table 15.7 Relation between n and Clock SMR Setting n 0 0 2 3 Clock W/2* /W* 1 2 CKS1 0 0 1 1 CKS0 0 1 0 1 /16 /64 Notes: 1. W/2 clock in active (medium-speed/high-speed) mode and sleep (medium-speed/highspeed) mode 2. W clock in subactive or subsleep mode In subactive or subsleep mode, the SCI3_1 and SCI3_2 can be operated only when CPU clock is W/2. 15.3.9 Serial Port Control Register (SPCR) SPCR selects the functions of the TXD32 and TXD31 pins. Bit 7 6 5 Bit Name SPC32 Initial Value 1 1 0 R/W R/W Description Reserved These bits are always read as 1 and cannot be modified. P32/TXD33 Pin Function Switch Selects whether pin P32/TXD32 is used as P32 or as TXD32. 0: P32 I/O pin 1: TXD32 output pin Set the TE32 bit in SCR32 after setting this bit to 1. 4 SPC31 0 R/W P42/TXD31 Pin Function Switch Selects whether pin P42/TXD31 is used as P42 or as TXD31. 0: P42 I/O pin 1: TXD31 output pin Set the TE bit in SCR after setting this bit to 1. Rev. 1.00 Dec. 18, 2006 Page 327 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Bit 3 Bit Name SCINV3 Initial Value 0 R/W R/W Description TXD32 Pin Output Data Inversion Switch Selects whether output data of the TXD32 pin is inverted or not. 0: Output data of TXD32 pin is not inverted. 1: Output data of TXD32 pin is inverted. 2 SCINV2 0 R/W TXD32 Pin Input Data Inversion Switch Selects whether input data of the TXD32 pin is inverted or not. 0: Output data of TXD32 pin is not inverted. 1: Output data of TXD32 pin is inverted. 1 SCINV1 0 R/W TXD31 Pin Output Data Inversion Switch Selects whether output data of the TXD31 pin is inverted or not. 0: Output data of TXD31 pin is not inverted. 1: Output data of TXD31 pin is inverted. 0 SCINV0 0 R/W RXD31 Pin Input Data Inversion Switch Selects whether input data of the RXD31 pin is inverted or not. 0: Input data of RXD31 pin is not inverted. 1: Input data of RXD31 pin is inverted. Note: When the serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying the serial port control register, modification must be made in a state in which data changes are invalidated. Rev. 1.00 Dec. 18, 2006 Page 328 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.3.10 IrDA Control Register (IrCR) IrCR controls the IrDA operation of the SCI3_1. Bit 7 Bit Name IrE Initial Value 0 R/W R/W Description IrDA Enable Selects whether the SCI3_1 I/O pins function as the SCI or IrDA. 0: TXD31/IrTXD or RXD31/IrRXD pin functions as TXD31 or RXD31 1: TXD31/IrTXD or RXD31/IrRXD pin functions as IrTXD or IrRXD 6 5 4 IrCKS2 IrCKS1 IrCKS0 0 0 0 R/W R/W R/W IrDA Clock Select If the IrDA function is enabled, these bits set the highpulse width when encoding the IrTXD output pulse. 000: Bit rate x 3/16 001: /2 010: /4 011: /8 100: /16 101: Setting prohibited 11x: Setting prohibited 3 to 0 0 Reserved These bits are always read as 0 and cannot be modified. [Legend] x: Don't care. Rev. 1.00 Dec. 18, 2006 Page 329 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous mode, synchronization is performed at the falling edge of the start bit during reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transfer data is latched at the center of each bit. Inside the SCI3, the transmitter and receiver are independent units, enabling full duplex. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. Table 15.8 shows the 16 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in SMR as shown in table 15.9. LSB Serial Start data bit Transmit/receive data MSB Parity bit 1 Stop bit Mark state 1 bit 5, 7, or 8 bits One unit of transfer data (character or frame) 1 bit, or none 1 or 2 bits Figure 15.2 Data Format in Asynchronous Communication Rev. 1.00 Dec. 18, 2006 Page 330 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.4.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK31 (SCK32) pin can be selected as the SCI3's serial clock source, according to the setting of the COM bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK31 (SCK32) pin, the clock frequency should be 16 times the bit rate used. For details on selection of the clock source, see table 15.10. When the SCI3 is operated on an internal clock, the clock can be output from the SCK31 (SCK32) pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transfer data, as shown in figure 15.3. Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 character (frame) Figure 15.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) Rev. 1.00 Dec. 18, 2006 Page 331 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Table 15.8 Data Transfer Formats (Asynchronous Mode) SMR CHR 0 PE 0 MP 0 STOP 0 1 START Serial Data Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 0 0 0 1 START 8-bit data STOP STOP 0 0 1 0 Setting prohibited 0 0 1 1 Setting prohibited 0 1 0 0 START 8-bit data P STOP 0 1 0 1 START 8-bit data P STOP STOP 0 1 1 0 START 5-bit data STOP 0 1 1 1 START 5-bit data STOP STOP 1 0 0 0 START 7-bit data STOP 1 0 0 1 START 7-bit data STOP STOP 1 0 1 0 Setting prohibited 1 0 1 1 Setting prohibited 1 1 0 0 START 7-bit data P STOP 1 1 0 1 START 7-bit data P STOP STOP 1 1 1 0 START 5-bit data P STOP 1 1 1 1 START 5-bit data P STOP STOP [Legend] START: Start bit STOP: Stop bit Parity bit P: Multiprocessor bit MPB: Rev. 1.00 Dec. 18, 2006 Page 332 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Table 15.9 SMR Settings and Corresponding Data Transfer Formats SMR Bit 7 COM 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 * * Asynchronous mode Clock synchronous mode 5-bit data No Yes 1 bit 2 bits 8-bit data No No No Asynchronous mode 5-bit data No No 1 bit 2 bits Setting prohibited Setting prohibited Yes 7-bit data No Mode Asynchronous mode Data Length 8-bit data Data Transfer Format Multiprocessor Parity Bit Bit No No Stop Bit Length 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits [Legend] *: Don't care. Rev. 1.00 Dec. 18, 2006 Page 333 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Table 15.10 SMR and SCR Settings and Clock Source Selection SMR Bit 7 COM 0 Bit 1 CKE1 0 SCR Bit 0 CKE0 0 1 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 1 External Clock synchronous Internal mode External Mode Asynchronous mode Transmit/Receive Clock Clock Source Internal SCK Pin Function I/O port (SCK31 or SCK32 pin not used) Outputs clock with same frequency as bit rate Inputs clock with frequency 16 times bit rate Outputs serial clock Inputs serial clock Reserved (Do not specify these combinations) Rev. 1.00 Dec. 18, 2006 Page 334 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.4.2 SCI3 Initialization Follow the flowchart as shown in figure 15.4 to initialize the SCI3. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. When the external clock is used in clock synchronous mode, the clock must not be supplied during initialization. [1] Start initialization Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock output is selected in asynchronous mode, clock is output immediately after CKE1 and CKE0 settings are made. When the clock output is selected at reception in clocked synchronous mode, clock is output immediately after CKE1, CKE0, and RE are set to 1. [2] [3] No 1-bit interval elapsed? Yes Set SPC32 (SPC31) bit in SPCR to 1 Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits. [4] [4] Set the data transfer format in SMR. Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Setting bits TE and RE enables the TXD31 (TXD32) and RXD31 (RXD32) pins to be used. Also set the RIE, TIE, TEIE, and MPIE bits, depending on whether interrupts are required. In asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit. Clear TE and RE bits in SCR to 0 [1] Set CKE1 and CKE0 bits in SCR3 Set data transfer format in SMR [2] Set value in BRR Wait [3] Figure 15.4 Sample SCI3 Initialization Flowchart Rev. 1.00 Dec. 18, 2006 Page 335 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.4.3 Data Transmission Figure 15.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI31 (TXI32) interrupt request is generated. Continuous transmission is possible because the TXI31 (TXI32) interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. 3. The SCI3 checks the TDRE flag at the timing for sending the stop bit. 4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. 6. Figure 15.6 shows a sample flowchart for transmission in asynchronous mode. Start bit Serial data 1 0 D0 D1 1 frame Transmit data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 1 frame D7 Parity Stop bit bit 0/1 1 Mark state 1 TDRE TEND LSI TXI31 (TXI32) operation interrupt request User generated processing TDRE flag cleared to 0 Data written to TDR TXI31 (TXI32) interrupt request generated TEI31 (TEI32) interrupt request generated Figure 15.5 Example SCI3 Operation in Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) Rev. 1.00 Dec. 18, 2006 Page 336 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Start transmission Set SPC32 (SPC31) bit in SPCR to 1 [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR [2] Yes All data transmitted? No Read TEND flag in SSR [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. (After the TE bit is set to 1, one frame of 1 is output, then transmission is possible.) [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [3] To output a break in serial transmission, after setting PCR to 1 and PDR to 0, clear the TE bit in SCR to 0. No TEND = 1 Yes No Break output? [3] Yes Clear PDR to 0 and set PCR to 1 Clear TE bit in SCR to 0 Figure 15.6 Sample Serial Transmission Flowchart (Asynchronous Mode) Rev. 1.00 Dec. 18, 2006 Page 337 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.4.4 Serial Data Reception Figure 15.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives data in RSR, and checks the parity bit and stop bit. * Parity check The SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even) set in bit PM in the serial mode register (SMR). * Stop bit check The SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked. * Status check The SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI31 (ERI32) interrupt request is generated. Receive data is not transferred to RDR. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI31 (ERI32) interrupt request is generated. 4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI31 (ERI32) interrupt request is generated. 5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI31 (RXI32) interrupt request is generated. Continuous reception is possible because the RXI31 (RXI32) interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed. Rev. 1.00 Dec. 18, 2006 Page 338 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Start bit Serial data 1 0 D0 D1 Receive data D7 1 frame Parity Stop Start bit bit bit 0/1 1 0 D0 Receive data D1 D7 1 frame Parity Stop bit bit 0/1 0 Mark state (idle state) 1 RDRF FER LSI operation User processing RXI31 (RXI32) RDRF cleared to 0 request 0 stop bit detected ERI request in response to framing error RDR data read Framing error processing Figure 15.7 Example SCI3 Operation in Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) Table 15.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.8 shows a sample flowchart for serial data reception. Table 15.11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * OER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains the state it had before data reception. However, note that if RDR is read after an overrun error has occurred in a frame because reading of the receive data in the previous frame was delayed, the RDRF flag will be cleared to 0. Rev. 1.00 Dec. 18, 2006 Page 339 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR No RDRF = 1 Yes [2] Read receive data in RDR [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically. [3] To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and read RDR. The RDRF flag is cleared automatically. [4] If a receive error occurs, read the OER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the input port corresponding to the RXD31 (RXD32) pin. Yes All data received? (A) No Clear RE bit in SCR to 0 Figure 15.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1) Rev. 1.00 Dec. 18, 2006 Page 340 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) [4] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0 Figure 15.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2) Rev. 1.00 Dec. 18, 2006 Page 341 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.5 Operation in Clock Synchronous Mode Figure 15.9 shows the general format for clock synchronous communication. In clock synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clock synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clock synchronous mode, the SCI3 receives data in synchronous with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clock synchronous mode, no parity or multiprocessor bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. 8-bit * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care One unit of transfer data (character or frame) * Figure 15.9 Data Format in Clock Synchronous Communications 15.5.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK31 (SCK32) pin can be selected, according to the setting of the COM bit in SMR and CKE0 and CKE1 bits in SCR. When the SCI3 is operated on an internal clock, the serial clock is output from the SCK31 (SCK32) pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 15.5.2 SCI3 Initialization Before transmitting and receiving data, the SCI3 should be initialized as described in a sample flowchart in figure 15.4. Rev. 1.00 Dec. 18, 2006 Page 342 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.5.3 Serial Data Transmission Figure 15.10 shows an example of SCI3 operation for transmission in clock synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI31 (TXI32) interrupt request is generated. 3. 8-bit data is sent from the TXD31 (TXD32) pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD31 (TXD32) pin. 4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI31 (TEI32) is generated. 7. The SCK31 (SCK32) pin is fixed high. Figure 15.11 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission. Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 1 frame TDRE TEND TXI31 (TXI32) LSI operation interrupt request generated User processing TDRE flag cleared to 0 Data written to TDR TXI31 (TXI32) interrupt request generated 1 frame TEI31 (TEI32) interrupt request generated Figure 15.10 Example of SCI3 Operation in Transmission in Clock Synchronous Mode Rev. 1.00 Dec. 18, 2006 Page 343 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Start transmission Set SPC32 (SPC31) bit in SPCR to 1 [1] [1] Read TDRE flag in SSR No TDRE = 1 [2] Yes Write transmit data to TDR Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. When clock output is selected and data is written to TDR, clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. [2] All data transmitted? No Yes Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR to 0 Figure 15.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode) Rev. 1.00 Dec. 18, 2006 Page 344 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.5.4 Serial Data Reception (Clock Synchronous Mode) Figure 15.12 shows an example of SCI3 operation for reception in clock synchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. 2. The SCI3 stores the received data in RSR. 3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI31 (ERI32) interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. 4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI31 (RXI32) interrupt request is generated. Serial clock Serial data Bit 7 Bit 0 1 frame Bit 7 Bit 0 Bit 1 1 frame Bit 6 Bit 7 RDRF OER LSI operation User processing RDRF flag RXI31 (RXI32) cleared interrupt to 0 request generated RDR data read RXI31 (RXI32)interrupt request generated RDR data has not been read (RDRF = 1) ERI interrupt request generated by overrun error Overrun error processing Figure 15.12 Example of SCI3 Reception Operation in Clock Synchronous Mode Rev. 1.00 Dec. 18, 2006 Page 345 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.13 shows a sample flowchart for serial data reception. Start reception [1] Read OER flag in SSR [1] [2] Yes OER = 1? [4] No Overrun error processing (Continued below) Read RDRF flag in SSR [2] [4] RDRF = 1? Yes Read receive data in RDR [3] No Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag and reading RDR should be finished. When data is read from RDR, the RDRF flag is automatically cleared to 0. If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Reception cannot be resumed if the OER flag is set to 1. Yes Data reception continued? No Clear RE bit in SCR to 0 Overrun error processing Clear OER flag in SSR to 0 Figure 15.13 Sample Serial Reception Flowchart (Clock Synchronous Mode) Rev. 1.00 Dec. 18, 2006 Page 346 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.5.5 Simultaneous Serial Data Transmission and Reception Figure 15.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction. Start transmission/reception Set SPC32 (SPC31) bit in SPCR to 1 No No Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the [1] Read TDRE flag in SSR TDRE flag is automatically cleared to 0. [2] Read SSR and check that the RDRF TDRE = 1 flag is set to 1, then read the receive data in RDR. Yes When data is read from RDR, the RDRF flag is automatically cleared to Write transmit data to TDR 0. [3] To continue serial transmission/ reception, before the MSB (bit 7) of Read OER flag in SSR the current frame is received, finish reading the RDRF flag, reading RDR. Yes Also, before the MSB (bit 7) of the OER = 1 [4] current frame is transmitted, read 1 from the TDRE flag to confirm that Overrun error processing No writing is possible. Then write data to TDR. When data is written to TDR, the Read RDRF flag in SSR [2] TDRE flag is automatically cleared to 0. When data is read from RDR, the RDRF flag is automatically cleared to RDRF = 1 0. [4] If an overrun error occurs, read the Yes OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Read receive data in RDR Transmission/reception cannot be resumed if the OER flag is set to 1. For overrun error processing, see figure 15.13. [3] [1] Yes Data transmission/reception continued? No Clear TE and RE bits in SCR to 0 Figure 15.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clock Synchronous Mode) Rev. 1.00 Dec. 18, 2006 Page 347 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.6 IrDA Operation IrDA operation can be used with the SCI3_1. Figure 15.19 shows an IrDA block diagram. If the IrDA function is enabled using the IrE bit in IrCR, the TXD31 and RXD31 pins in the SCI3_1 are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function as the IrTXD and IrRXD pins). Connecting these pins to the infrared data transceiver/receiver achieves infrared data communication based on the system defined by the IrDA standard version 1.0. In the system defined by the IrDA standard version 1.0, communication is started at a transfer rate of 9600 bps, which can be modified as required. The IrDA interface provided by this LSI does not incorporate the capability of automatic modification of the transfer rate; the transfer rate must be modified through programming. IrDA TXD31/IrTXD RXD31/IrRXD Phase inversion Phase inversion Pulse encoder Pulse decoder SCI3_1 TXD RXD IrCR Figure 15.15 IrDA Block Diagram 15.6.1 Transmission During transmission, the output signals from the SCI (UART frames) are converted to IR frames using the IrDA interface (see figure 15.16). For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in IrCR. The high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%) x bit rate or (3/16 x bit rate) +1.08 s at maximum. For example, when the frequency of system clock is 10 MHz, a high-level pulse width of at least 2.82 s to 3.2 s can be specified. For serial data of level 1, no pulses are output. Rev. 1.00 Dec. 18, 2006 Page 348 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) UART frame Start bit Data Stop bit 0 1 0 1 0 0 1 1 0 1 Transmission Reception IR frame Start bit Data Stop bit 0 Bit cycle 1 0 1 0 0 1 1 0 1 Pulse width is 1.6 s to 3/16 bit cycle Figure 15.16 IrDA Transmission and Reception 15.6.2 Reception During reception, IR frames are converted to UART frames using the IrDA interface before inputting to the SCI3_1. Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 2.82 s, the minimum width allowed, the pulse is recognized as level 0. Rev. 1.00 Dec. 18, 2006 Page 349 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.6.3 High-Level Pulse Width Selection Table 15.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 15.12 IrCKS2 to IrCKS0 Bit Settings Operating Frequency (MHz) 2 2.097152 2.4576 3 3.6864 4.9152 5 6 6.144 7.3728 8 9.8304 10 2400 78.13 010 010 010 011 011 011 011 100 100 100 100 100 100 Bit Rate (bps) (Upper Row) / Bit Interval x 3/16 (s) (Lower Row) 9600 19.53 010 010 010 011 011 011 011 100 100 100 100 100 100 19200 9.77 010 010 010 011 011 011 011 100 100 100 100 100 100 38400 4.88 010 010 010 011 011 011 011 100 100 100 100 100 100 Rev. 1.00 Dec. 18, 2006 Page 350 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.7 Interrupt Requests The SCI3 creates the following six interrupt requests: transmit end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 15.13 shows the interrupt sources. Table 15.13 SCI3 Interrupt Requests Interrupt Requests Receive Data Full Transmit Data Empty Transmission End Receive Error Abbreviation RXI TXI TEI ERI Interrupt Sources Setting RDRF in SSR Setting TDRE in SSR Setting TEND in SSR Setting OER, FER, and PER in SSR Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR. When the TDRE bit in SSR is set to 1, a TXI31 (TXI32) interrupt is requested. When the TEND bit in SSR is set to 1, a TEI31 (TEI32) interrupt is requested. These two interrupts are generated during transmission. The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR is set to 1 before transferring the transmit data to TDR, a TXI31 (TXI32) interrupt request is generated even if the transmit data is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR is set to 1 before transferring the transmit data to TDR, a TEI31 (TEI32) interrupt request is generated even if the transmit data has not been sent. It is possible to make use of the most of these interrupt requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the generation of these interrupt requests (TXI31 and TEI31), set the enable bits (TIE and TEIE) that correspond to these interrupt requests to 1, after transferring the transmit data to TDR. When the RDRF bit in SSR is set to 1, an RXI31 (RXI32) interrupt is requested, and if any of bits OER, PER, and FER is set to 1, an ERI31 (ERI32) interrupt is requested. These two interrupt requests are generated during reception. The SCI3 can carry out continuous reception using an RXI31 (RXI32) and continuous transmission using a TXI31 (TXI32). These interrupts are shown in table 15.14. Rev. 1.00 Dec. 18, 2006 Page 351 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) Table 15.14 Transmit/Receive Interrupts Interrupt RXI31 (RXI32) Flags RDRF RIE Interrupt Request Conditions When serial reception is performed normally and receive data is transferred from RSR to RDR, bit RDRF is set to 1, and if bit RIE is set to 1 at this time, an RXI31 (RXI32) is enabled and an interrupt is requested. (See figure 15.17 (a).) When TSR is found to be empty (on completion of the previous transmission) and the transmit data placed in TDR is transferred to TSR, bit TDRE is set to 1. If bit TIE is set to 1 at this time, a TXI31 (TXI32) is enabled and an interrupt is requested. (See figure 15.17 (b).) When the last bit of the character in TSR is transmitted, if bit TDRE is set to 1, bit TEND is set to 1. If bit TEIE is set to 1 at this time, a TEI31 (TEI32) is enabled and an interrupt is requested. (See figure 15.17 (c).) Notes The RXI31 (RXI32) interrupt routine reads the receive data transferred to RDR and clears bit RDRF to 0. Continuous reception can be performed by repeating the above operations until reception of the next RSR data is completed. The TXI31 (TXI32) interrupt routine writes the next transmit data to TDR and clears bit TDRE to 0. Continuous transmission can be performed by repeating the above operations until the data transferred to TSR has been transmitted. A TEI31 (TEI32) indicates that the next transmit data has not been written to TDR when the last bit of the transmit character in TSR is transmitted. TXI31 (TXI32) TDRE TIE TEI31 (TEI32) TEND TEIE Rev. 1.00 Dec. 18, 2006 Page 352 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) RDR RDR RSR (reception in progress) RXD31 (RXD32) pin RXD31 (RXD32) pin RSR (reception completed, transfer) RDRF = 0 RDRF (RXI request when RIE = 1) Figure 15.17 (a) RDRF Setting and RXI Interrupt TDR (next transmit data) TDR TSR (transmission in progress) TXD31 (TXD32) pin TXD31 (TXD32) pin TSR (transmission completed, transfer) TDRE = 0 TDRE 1 (TXI request when TIE = 1) Figure 15.17 (b) TDRE Setting and TXI Interrupt TDR TDR TSR (transmission in progress) TXD31 (TXD32) pin TXD31 (TXD32) pin TSR (transmission completed) TEND = 0 TEND (TEI request when TEIE = 1) Figure 15.17 (c) TEND Setting and TEI Interrupt Rev. 1.00 Dec. 18, 2006 Page 353 of 568 REJ09B0348-0100 1 1 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.8 15.8.1 Usage Notes Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RXD31 (RXD32) pin value directly. In a break, the input from the RXD31 (RXD32) pin becomes all 0, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 15.8.2 Mark State and Break Sending When TE is 0, the TXD31 (TXD32) pin is used as an I/O port whose direction (input or output) and level are determined by PCR and PDR. This can be used to set the TXD31 (TXD32) pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TXD31 (TXD32) pin becomes an I/O port, and 1 is output from the TXD31 (TXD32) pin. To send a break during serial transmission, first set PCR to 1 and PDR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TXD31 (TXD32) pin becomes an I/O port, and 0 is output from the TXD31 (TXD32) pin. 15.8.3 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only) Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Rev. 1.00 Dec. 18, 2006 Page 354 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 15.18. Thus, the reception margin in asynchronous mode is given by formula (1) below. 1 D - 0.5 M = (0.5 - )- - (L - 0.5) F x 100(%) 2N N ... Formula (1) Where N: D: L: F: Ratio of bit rate to clock (N = 16) Clock duty (D = 0.5 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. 16 clocks 8 clocks 0 Internal basic clock Receive data (RXD31/RXD32) Synchronization sampling timing Data sampling timing 7 15 0 7 15 0 Start bit D0 D1 Figure 15.18 Receive Data Sampling Timing in Asynchronous Mode Rev. 1.00 Dec. 18, 2006 Page 355 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.8.5 Note on Switching SCK31 (SCK32) Pin Function If pin SCK31 (SCK32) is used as a clock output pin by the SCI3 in clock synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock () cycle immediately after it is switched. This can be prevented by either of the following methods according to the situation. (1) When SCK31 (SCK32) Function is Switched from Clock Output to Non Clock-Output When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR to 1 and 0, respectively. In this case, bit COM in SMR should be left 1. The above prevents the SCK31 (SCK32) pin from being used as a general input/output pin. To avoid an intermediate level of voltage from being applied to the SCK31 (SCK32) pin, the line connected to the SCK31 (SCK32) pin should be pulled up to the VCC level via a resistor, or supplied with output from an external device. (2) When SCK31 (SCK32) Function is Switched from Clock Output to General Input/Output When stopping data transfer, 1. Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR to 1 and 0, respectively. 2. Clear bit COM in SMR to 0 3. Clear bits CKE1 and CKE0 in SCR to 0. Note that special care is also needed here to avoid an intermediate level of voltage from being applied to the SCK31 (SCK32) pin. 15.8.6 Relation between Writing to TDR and Bit TDRE Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. When the SCI3 transfers data from TDR to TSR, bit TDRE is set to 1. Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost if it has not yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR only once (not two or more times). Rev. 1.00 Dec. 18, 2006 Page 356 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.8.7 Relation between RDR Reading and bit RDRF In a receive operation, the SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred. When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if RDR is read more than once, the second and subsequent read operations will be performed while bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0, if the read operation coincides with completion of reception of a frame, the next frame of data may be read. This is shown in figure 15.19. Frame 1 Communication line Data 1 Frame 2 Data 2 Frame 3 Data 3 RDRF RDR Data 1 (A) RDR read Data 2 (B) RDR read Data 1 is read at point (A) Data 2 is read at point (B) Figure 15.19 Relation between RDR Read Timing and Data In this case, only a single RDR read operation (not two or more) should be performed after first checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is sufficient margin in an RDR read operation before reception of the next frame is completed. To be precise in terms of timing, the RDR read should be completed before bit 7 is transferred in clock synchronous mode, or before the STOP bit is transferred in asynchronous mode. 15.8.8 Transmit and Receive Operations when Making State Transition Make sure that transmit and receive operations have completely finished before carrying out state transition processing. Rev. 1.00 Dec. 18, 2006 Page 357 of 568 REJ09B0348-0100 Section 15 Serial Communication Interface 3 (SCI3, IrDA) 15.8.9 Setting in Subactive or Subsleep Mode In subactive or subsleep mode, the SCI3 can operate only when the CPU clock is W/2. The SA1 bit in SYSCR2 should be set to 1. 15.8.10 Oscillator when Serial Communication Interface 3 is Used (Supported only by the Mask ROM Version) When serial communication interface 3 is used in the mask ROM version, do not use the on-chip oscillator. For details on selecting the system clock oscillator or on-chip oscillator, see section 5.2.4, On-Chip Oscillator Selection Method (Supported only by the Mask ROM Version). Rev. 1.00 Dec. 18, 2006 Page 358 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) Section 16 Serial Communication Interface 4 (SCI4) The serial communication interface 4 (SCI4) can handle clocked synchronous serial communication with the 8-bit buffer. The SCI4 is supported only by the F-ZTAT version. When the on-chip emulator debugger etc. is used, the SCK4, SI4, and SO4 pins in SCI4 are used by the system. Therefore the SCI4 is not available for the user. 16.1 Features * Eight internal clocks (/1024, /256, /64, /32, /16, /8, /4, /2) or external clock can be selected as a clock source. * Receive error detection: Overrun errors detected * Four interrupt sources Transmit-end, transmit-data-empty, receive-data-full, and overrun error * Full-duplex communication capability Buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * When the on-chip emulator debugger etc. is not used, the SCI4 is available for the user. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 6.4, Module Standby Function.) Rev. 1.00 Dec. 18, 2006 Page 359 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) Figure 16.1 shows a block diagram of the SCI4. PSS SCK4 Transmit/receive control circuit SCSR4 SCR4 TDR4 SI4 SO4 SR4 RDR4 [Legend] SCSR4: Serial control status register 4 SCR4: Serial control register 4 TDR4: Transmit data register 4 SR4: Shift register 4 RDR4: Receive data register 4 TEI TXI RXI ERI Figure 16.1 Block Diagram of SCI4 16.2 Input/Output Pins Table 16.1 shows the SCI4 pin configuration. Table 16.1 Pin Configuration Pin Name SCI4 clock SCI4 data input SCI4 data output Abbreviation SCK4 SI4 SO4 I/O I/O Input Output Function SCI4 clock input/output SCI4 receive data input SCI4 transmit data output Rev. 1.00 Dec. 18, 2006 Page 360 of 568 REJ09B0348-0100 Internal data bus Section 16 Serial Communication Interface 4 (SCI4) 16.3 Register Descriptions The SCI4 has the following registers. * * * * * Serial control register 4 (SCR4) Serial control/status register 4 (SCSR4) Transmit data register 4 (TDR4) Receive data register 4 (RDR4) Shift Register 4 (SR4) Serial Control Register 4 (SCR4) 16.3.1 SCR4 enables or disables interrupt requests and controls SCI4 transfer operations. Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable Enables or disables a transmit data empty interrupt (TXI) request when serial transmit data is transferred from TDR4 to SR4 and the TDRE flag in SCSR4 is set to 1. TXI can be cleared by clearing the TDRE flag in SCSR4 to 0 after the flag is read as 1 or clearing this bit to 0. 0: Transmit data empty interrupt (TXI) request disabled 1: Transmit data empty interrupt (TXI) request enabled 6 RIE 0 R/W Receive Interrupt Enable Enables or disables a receive data full interrupt (RXI) request and receive error interrupt (ERI) request when serial receive data is transferred from SR4 to RDR4 and the RDRF flag in SCSR4 is set to 1. RXI and ERI can be cleared by clearing the RDRF or ORER flag in SCSR4 to 0 after the flag is read as 1 or clearing this bit to 0. 0: Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled 1: Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Rev. 1.00 Dec. 18, 2006 Page 361 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) Bit 5 Bit Name TEIE Initial Value 0 R/W R/W Description Transmit End Interrupt Enable Enables or disables a transmit end interrupt (TEI) request when there is no valid transmit data in TDR4 during transmission of MSB data. TEI can be cleared by clearing the TEND flag in SCSR4 to 0 after the flag is read as 1 or clearing this bit to 0. 0: Transmit end interrupt (TEI) request disabled 1: Transmit end interrupt (TEI) request enabled 4 SOL 0 R/W Extended Data Sets the output level of the SO4 pin. When this bit is read, the output level of the SO4 pin is read. The output of the SO4 pin retains the value of the last bit of transmit data after transmission is completed. However, if this bit is changed before or after transmission, the output level of the SO4 pin can be changed. When the output level of the SO4 pin is changed, the SOLP bit should be cleared to 0 and the MOV instruction should be used. Note that this bit should not be changed during transmission because incorrect operation may occur. [When reading] 0: The output level of the SO4 pin is low. 1: The output level of the SO4 pin is high. [When writing] 0: The output level of the SO4 pin is changed to low. 1: The output level of the SO4 pin is changed to high. 3 SOLP 1 R/W SOL Write Protect Controls change of the output level of the SO4 pin due to the change of the SOL bit. When the output level of the SO4 pin is changed, the setting of SOL = 1 and SOLP = 0 or SOL = 0 and SOLP = 0 is made by the MOV instruction. This bit is always read as 1. 0: When writing, the output level is changed according to the value of the SOL pin. 1: When reading, this bit is always read as 1 and cannot be modified. Rev. 1.00 Dec. 18, 2006 Page 362 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) Bit 2 Bit Name SRES Initial Value 0 R/W R/W Description Forcible Reset When the internal sequencer is forcibly initialized, 1 should be written to this bit. When 1 is written to this flag, the internal sequencer is forcibly reset and then this flag is automatically cleared to 0. Note that the values of the internal registers are retained. (The TDRE flag in SCSR4 is set to 1 and the RDRF, ORER, and TEND flags are cleared to 0. The TE and RE bits in SCR4 are cleared to 0.) 0: Normal operation 1: Internal sequencer is forcibly reset 1 TE 0 R/W Transmit Enable Enables or disables start of the SCI4 serial transmission. When this bit is cleared to 0, the TERE flag in SCSR4 is fixed to 1. When transmit data is written to TDR4 while this bit is set to 1, the TDRE flag in SCSR4 is automatically cleared to 0 and serial data transmission is started. 0: Transmission disabled (SO4 pin functions as I/O port) 1: Transmission enabled (SO4 pin functions as transmit data pin) 0 RE 0 R/W Receive Enable Enables or disables start of the SCI4 serial reception. Note that the RDRF and ORER flags in SCSR4 are not affected even if this bit is cleared to 0, and retain their previous state. Serial data reception is started when the synchronous clock input is detected while this bit is set to 1 (when an external clock is selected). When an internal clock is selected, the synchronous clock is output and serial data reception is started. 0: Reception disabled (SI4 pin functions as I/O port) 1: Reception enabled (SI4 pin functions as receive data pin) Rev. 1.00 Dec. 18, 2006 Page 363 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) 16.3.2 Serial Control/Status Register 4 (SCSR4) SCSR4 indicates the operating state and error state, selects the clock source, and controls the prescaler division ratio. SCSR4 can be read from or written to by the CPU at any time. 1 cannot be written to flags TDRE, RDRF, ORER, and TEND. To clear these flags to 0, 1 should be read from them in advance. Bit 7 Bit Name TDRE Initial Value 1 R/W Description R/(W)* Transmit Data Empty Indicates that data is transferred from TDR4 to SR4 and the next serial transmit data can be written to TDR4. [Setting conditions] * * When the TE bit in SCR4 is 0 When data is transferred from TDR4 to SR4 and data can be written to TDR4 When 0 is written to TDRE after reading TDRE = 1 When data is written to TDR4 [Clearing conditions] * * 6 RDRF 0 R/(W)* Receive Data Full Indicates that the receive data is stored in RDR4. [Setting condition] * When serial reception ends normally and receive data is transferred from SR4 to RDR4 When 0 is written to RDRF after reading RDRF = 1 When data is read from RDR4 [Clearing conditions] * * Rev. 1.00 Dec. 18, 2006 Page 364 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) Bit 5 Bit Name ORER Initial Value 0 R/W Description R/(W)* Overrun Error Indicates that an overrun error occurs during reception and then abnormal termination occurs. In transfer mode, the output level of the SO4 pin is fixed to low while this flag is set to 1. When the RE bit in SCR4 is cleared to 0, the ORER flag is not affected and retains its previous state. When RDR4 retains the receive data it held before the overrun error occurred, and data received after the error is lost. Reception cannot be continued with the ORER flag set to 1, and transmission cannot be continued either. [Setting condition] * When the next serial reception is completed while RDRF = 1 When 0 is written to ORER after reading ORER = 1 [Clearing condition] * 4 TEND 0 R/(W)* Transmit End Indicates that the TDRE flag has been set to 1 at transmission of the last bit of transmit data. [Setting condition] * When TDRE = 1 at transmission of the last bit of transmit data When 0 is written to TEND after reading TEND = 1 When data is written to TDR4 with an instruction [Clearing conditions] * * 3 2 1 0 CKS3 CKS2 CKS1 CKS0 1 0 0 0 R/W R/W R/W R/W Clock Source Select and Pin Function Select the clock source to be supplied and set the input/output for the SCK4 pin. The prescaler division ratio and transfer clock cycle when an internal clock is selected are shown in table 16.2. When an external clock is selected, the external clock cycle should be at least 4/. Note: * Only 0 can be written to clear the flag. Rev. 1.00 Dec. 18, 2006 Page 365 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) Table 16.2 shows a prescaler division ratio and transfer clock cycle. Table 16.2 Prescaler Division Ratio and Transfer Clock Cycle (Internal Clock) Bit 3 CKS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 CKS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Prescaler Division Ratio /1024 /256 /64 /32 /16 /8 /4 /2 Transfer Clock Cycle = 5 MHz 204.8 s 51.2 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s = 2.5 MHz 409.6 s 102.4 s 25.6 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s External clock Function Clock Resource Internal clock Internal clock Internal clock Internal clock Internal clock Internal clock Internal clock Internal clock Pin Function SCK4 output pin SCK4 output pin SCK4 output pin SCK4 output pin SCK4 output pin SCK4 output pin SCK4 output pin SCK4 output pin I/O port (initial value) I/O port I/O port I/O port I/O port I/O port I/O port SCK4 input pin Rev. 1.00 Dec. 18, 2006 Page 366 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) 16.3.3 Transmit Data Register 4 (TDR4) TDR4 is an 8-bit register that stores data for serial transmission. When the SCI4 detects that SR4 is empty, it transfers the transmit data written in TDR4 to SR4 and starts serial transmission. If the next transmit data is written to TDR4 while serial data in SR4 is being transmitted, continuous serial transmission is possible. TDR4 can be read from or written to by the CPU at any time. TDR4 is initialized to H'FF. 16.3.4 Receive Data Register 4 (RDR4) RDR4 is an 8-bit register that stores receive data. When the SCI4 has received one byte of serial data, it transfers the received serial data from SR4 to RDR4, where it is stored. Then receive operation is completed. After this, SR4 is receive-enabled. RDR4 cannot be written to by the CPU. RDR4 is initialized to H'00. 16.3.5 Shift Register 4 (SR4) SR4 is a register that receives or transmits serial data. SR4 cannot be directly read from or written to by the CPU. Rev. 1.00 Dec. 18, 2006 Page 367 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) 16.4 Operation The SCI4 is a serial communication interface that transmits and receives data in synchronization with a clock pulse and is suitable for high-speed serial communication. The data transfer format is fixed to 8-bit data. The internal clock or external clock can be selected as a clock source. An overrun error during reception can be detected. The transmit and receive units are configured with double buffering mechanism. Since the mechanism enables to write data during transmission and to read data during reception, data is consecutively transmitted and received. 16.4.1 Clock The eight internal clocks or an external clock can be selected as a transfer clock. When the external clock is selected, the SCK4 pin is a clock input pin. When the internal clock is selected, the SCK4 pin is a synchronous clock output pin. The synchronous clock is output eight pulses for 1-character transmission or reception. While neither transmission nor reception is being performed, the signal is fixed high. When the internal clock or external clock is not selected according to the combination of the CKS3 to CKS0 bits in SCSR4, the SCK4 pin functions as an I/O port. 16.4.2 Data Transfer Format Figure 16.2 shows the SCI4 transfer format. SCK4 SO4/SI4 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 16.2 Data Transfer Format In clocked synchronous communication, data on the communication line is output from the falling edge to the next falling edge of the synchronous clock. The data is guaranteed to be settled at the rising edge of the synchronous clock. One character starts with the LSB and ends with the MSB. After transmitting the MSB, the communication line retains the MSB level. The SCI4 latches data at the rising edge of the synchronous clock on reception. The data transfer format is fixed to 8-bit data. While transmission is stopped, the output level on the SO4 pin can be changed by the SOL setting in SCR4. Rev. 1.00 Dec. 18, 2006 Page 368 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) 16.4.3 Data Transmission/Reception Before data transmission and reception, clear the TE and RE bits in SCR4 to 0 and then initialize as the following procedure of figure 16.3. Note: Before changing operating modes or communication format, the TE and RE bits must be cleared to 0. Clearing the TE bit to 0 sets the TDRE flag to 1. Note that clearing the RE bit to 0 does not affect the RDRF or ORER flag and the contents of RDR4. When the external clock is used, the clock must not be supplied during operation including initialization. Start of Initialization Clear TE and RE bits in SCR4 to 0 Clear CKS3 to CKS0 bits in SCSR4 to 0 Set TE and RE bits in SCR4 to 1. Set RIE, TIE, and TEIE bits. Figure 16.3 Flowchart Example of SCI4 Initialization Rev. 1.00 Dec. 18, 2006 Page 369 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) 16.4.4 Data Transmission Figure 16.4 shows an example flowchart of data transmission. Data transmission should be performed as the following procedure after the SCI4 initialization. Initialization [1] [1] Pin SO4 functions as output pin for transmit data After reading SCSR4 and confirming TDRE = 1, write transmit data in TDR4. Writing data in TDR4 clears the TDRE bit to 0 automatically. At this time, the clock is output to start data transmission. To consecutively transmit data, read TDRE = 1 to confirm that TDR4 is ready. After that, write data in TDR4. Writing data in TDR4 clears the TDRE bit to 0 automatically. Start transmission (TE = 1) [2] [2] [3] Read TDRE in SCSR4 TDRE = 1? Yes Write transmit data in TDR4 No TDRE bit cleared to 0 automatically Data transferred from TDR4 to SR4 Start transmission by setting TDRE bit to 1 Transmission will continue? No Read TEND in SCSR4 Yes [3] TEND = 1? Yes TEI occurs (TEIE = 1) No Clear TE bit in SCR4 to 0 Note: Hatching area indicates SCI internal operation. Figure 16.4 Flowchart Example of Data Transmission Rev. 1.00 Dec. 18, 2006 Page 370 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) During transmission, the SCI4 operates as shown below. 1. The SCI4 sets the TE bit to 1 and clears the TDRE flag to 0 when transmit data is written to in TDR4 to transmit data from TDR4 to SR4. After that, the SCI4 sets the TDRE flag to 1 to start transmission. At this time, when the TIE bit in SCR4 is set to 1, a TXI is generated. 2. In clock output mode, the SCI4 outputs eight pulses of the synchronous clock. When the external clock is selected, the SCI4 outputs data in synchronization with the input clock. 3. Serial data is output from the LSB (bit 0) to MSB (bit 7) on pin SO4. The SCI4 checks the TDRE flag at the timing of outputting the MSB (bit 7). 4. When TDRE = 0, data in TDR4 is transmitted to SR4 and then the data of the next frame starts to be transmitted. When TDRE = 1, the SCI4 sets the TEND bit to 1 and holds the output level after transmitting the MSB (bit 7). At this time, when the TEIE bit in SCR4 is set to 1, a TEI is generated. 5. After the transmission, the output level on pin SCK4 is fixed high. Note: Transmission cannot be performed when the error flag (ORER) which indicates the data reception status is set to 1. Before transmission, confirm that the ORER flag is cleared to 0. Figure 16.5 shows the example of transmission operation. Synchronous clock Serial data Bit 0 Bit 1 1 frame Bit 7 Bit 0 Bit 1 1 frame Bit 6 Bit 7 TDRE TEND TXI generated TDRE cleared Data written to TDR4 TXI generated TEI generated LSI operation User operation Figure 16.5 Transmit Operation Example Rev. 1.00 Dec. 18, 2006 Page 371 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) 16.4.5 Data Reception Figure 16.6 shows an example flowchart of data reception. Data reception should be performed as the following procedure after the SCI4 initialization. Initialization Start reception (RE = 1) [1] [1] Read ORER in SCSR4 [2] ORER = 1? No Read RDRF in SCSR4 Yes [3] Error processing (Shown below) [4] Pin SI4 functions as input pin for receive data [2][3] When a reception error occurs, read the ORER flag in SCSR4 and then clears the ORER flag to 0 after executing the error processing. When the ORER flag is set to 1, both transmission and reception cannot be restarted. [4] After reading SCSR4 and confirming RDRF = 1, read the receive data in RDR4. The RDRF flag is automatically cleared to 0. Changes in the RDRF flag from 0 to 1 can be notified by an RXI interrupt. [5] To consecutively receive data, reading the RDRF flag and RDR4 must be completed before receiving the MSB (bit 7) of the current frame. No RDRF = 1? Yes Read received data in RDR4 RDRF cleared to 0 automatically Yes Data transfer will continue? No Clear RE bit in SCR4 to 0 Error processing Overrun error processing [5] [3] Clear ORER flag in SCSR4 to 0 Note: Hatching area indicates SCI internal operation. Figure 16.6 Flowchart Example of Data Reception Rev. 1.00 Dec. 18, 2006 Page 372 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) During reception, the SCI4 operates as shown below. 1. The SCI4 initialization is performed in synchronization with the synchronous clock input or output and starts reception. 2. The SCI4 stores received data from the LSB to MSB of SR4. 3. After reception, the SCI4 checks that RDRF = 0 and whether receive data is ready for being transferred from SR4 to RDR4. 4. When confirms that an overrun error has not occurred, the RDRF bit is set to 1 and the received data is stored in RDR4. At this time, when the RIE bit in SCR4 is set to 1, an RXI is generated. When an overrun error is detected by checking, the ORER flag is set to 1. The RDRF bit retains the previously set value. If the RIE bit in SCR4 is set to 1, an ERI is generated. 5. An overrun error is detected when the next data reception is completed with the RDRF bit in SCSR4 set to 1. The received data is not transferred from SR4 to RDR4. Note: Reception cannot be performed when the error flag is set to 1. Before reception, confirm that the ORER and RDRF flags are cleared to 0. Figure 16.7 shows an operation example of reception. Synchronous clock Serial data Bit 7 Bit 0 1 frame Bit 7 Bit 0 Bit 1 1 frame Bit 6 Bit 7 RDRF ORER RXI generated RDRF cleared Data read from RDR4 RXI generated RDR4 has not been read from (RDRF = 1) ERI generated by overrun error Overrun error processing LSI operation User operation Figure 16.7 Receive Operation Example Rev. 1.00 Dec. 18, 2006 Page 373 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) 16.4.6 Simultaneous Data Transmission and Reception Figure 16.8 shows an example flowchart of simultaneous data transmission and reception. Simultaneous data transmission and reception should be performed as the following procedure after the SCI4 initialization. [1] Pin SO4 functions as output pin for transmit data and pin SI4 functions as input pin for receive data. Simultaneous transmission and reception is enabled. After reading SCSR4 and confirming TDRE = 1, write transmit data in TDR4. Writing data in TDR4 clears the TDRE bit to 0 automatically. At this time, the clock is output to start data transfer. When a reception error occurs, read the ORER flag in SCSR4 and then clear the ORER flag to 0 after executing the error processing. When the ORER flag is set to 1, both transmission and reception cannot be restarted. After reading SCSR4 and confirming RDRF = 1, read receive data in RDR4 and clear the RDRF flag to 0. An RXI interrupt can also be used to confirm that the RDRF flag value has been changed from 0 to 1. To consecutively transmit and receive data, the following operation must be completed: reading the RDRF flag and reading RDR4 before receiving the MSB (bit 7) of the current frame: confirming that TDR4 is ready for writing by reading TDRE = 1 before transmitting the MSB (bit 7) and writing data to TDR4 to clear the TDRE flag to 0. Initialization Start transmission (TE = 1, RE = 1) [1] [2] Read TDRE in SCSR4 [2] TDRE = 1? Yes Write transmit data in TDR4 No [3] [4] TDRE bit cleared to 0 automatically Data transferred from TDR4 to SR4 [5] Start transmission/reception by setting TDRE bit to 1 Read ORER in SCSR4 ORER = 1? No Read RDRF in SCSR4 Yes Error processing [4] [3] No RDRF = 1? Yes Read received data in RDR4 RDRF cleared to 0 automatically Data transfer will continue? No Clear TE and RE bits in SCR4 to 0 Yes [5] Note: Hatching area indicates SCI internal operation. Figure 16.8 Flowchart Example of Simultaneous Transmission and Reception Rev. 1.00 Dec. 18, 2006 Page 374 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) Notes: 1. When switching from transmission to simultaneous data transmission and reception, confirm that the SCI4 completes transmission and both the TDRE and TEND bits are set to 1. After that, clear the TE bit to 0 and then set both the TE and RE bits to 1. 2. When switching from reception to simultaneous data transmission and reception, confirm that the SCI4 completes reception and both the RDRF and ORER flags are cleared to 0 after clearing the RE bit to 0. After that, set both the TE and RE bits to 1. 16.5 Interrupt Sources The SCI4 has four interrupt sources: transmit end, transmit data empty, receive data full, and receive error (overrun error). Table 16.3 lists the descriptions of the interrupt sources. Table 16.3 SCI4 Interrupt Sources Abbreviation RXI TXI TEI ERI Condition RIE = 1 TIE = 1 TEIE = 1 RIE = 1 Interrupt Source Receive data full (RDRF) Transmit data empty (TDRE) Transmit end (TEND) Receive error (ORER) The interrupt requests can be enabled/disabled by the TIE and RIE bits in SCR4. When the TDRE flag in SCSR4 is set to 1, a TXI is generated. When the TEND bit in SCSR4 is set to 1, a TEI is generated. These two interrupt requests are generated during transmission. The TDRE flag in SCSR4 is initialized to 1. Therefore, if a TXI request is enabled by setting the TIE bit in SCR4 to 1 before transmit data is transferred to TDR4, a TXI is generated even when transmit data is not ready. If transmit data is transferred to TDR4 in the interrupt handling routine, these interrupt requests can be effectively used. To avoid the occurrence of the interrupt requests (TXI and TEI), clear the corresponding interrupt enable bits (TIE and TEIE) to 0 after transmit data is transferred to TDR4. When the RDRF bit in SCSR4 is set to 1, an RXI is generated. When the ORER flag is set to 1, an ERI is generated. These two interrupt requests are generated during reception. Rev. 1.00 Dec. 18, 2006 Page 375 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) 16.6 Usage Notes When using the SCI4, keep in mind the following. 16.6.1 Relationship between Writing to TDR4 and TDRE The TDRE flag in SCSR4 is a status flag that indicates that data to be transmitted has not been stored in TDR4. When writing data to TDR4, the TDRE flag is automatically cleared to 0. The TDRE flag is set to 1 when the SCI4 transfers data from TDR4 to SR4. Data is written to TDR4 regardless of the TDRE flag value. However, if data is written to TDR4 with TDRE = 0, the previous data is lost unless the previous data has been transferred to SR4. Accordingly, to ensure transmission, writing transmit data to TDR4 must be performed once after confirming that the TDRE flag has been set to 1. (Do not write more than once.) 16.6.2 Receive Error Flag and Transmission While the receive error flag (ORER) is set to 1, transmission cannot be started even if the TDRE flag is cleared to 0. To start transmission, the ORER flag must be cleared to 0. Note that the ORER flag cannot be cleared to 0 even if the RE bit is cleared to 0. 16.6.3 Relationship between Reading RDR4 and RDRF The SCI4 always checks the RDRF flag status during reception. When the RDRF flag is cleared to 0 at the end of a frame, the reception is completed without error. When the RDRF flag is set to 1, it indicates that an overrun has occurred. Since reading RDR4 clears the RDRF flag to 0 automatically, if RDR4 is read twice or more, the data is read with the RDRF flag cleared to 0. In this case, when the timing of the read operation matches that of the data reception of the next frame, the read data may be the next frame data. Figure 16.9 shows this operation. Rev. 1.00 Dec. 18, 2006 Page 376 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) Frame 1 Number of transfer Data 1 Frame 2 Data 2 Frame 3 Data 3 RDRF RDR4 Data 1 (A) RDR4 read (B) Data 2 RDR4 read At the timing of (A), data 1 is read. At the timing of (B), data 2 is read. Figure 16.9 Relationship between Reading RDR4 and RDRF In this case, RDR4 must be read only once after confirming RDRF = 1. If reading RDR4 twice or more, store the read data in the RAM, and use the stored data. In addition, there should be a margin from the timing of reading RDR4 to completion of the next frame reception. (Reading RDR4 should be completed before the bit 7 transfer.) 16.6.4 SCK4 Output Waveform when Internal Clock of /2 is Selected When the internal clock of /2 is selected by the CKS3 to CKS0 bits in SCSR4 and continuous transmission or reception is performed, one pulse of high period is lengthened after eight pulses of the clock has been output as shown in figure 16.10. SCK4 SO4/SI4 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Figure 16.10 Transfer Format when Internal Clock of /2 is Selected Rev. 1.00 Dec. 18, 2006 Page 377 of 568 REJ09B0348-0100 Section 16 Serial Communication Interface 4 (SCI4) Rev. 1.00 Dec. 18, 2006 Page 378 of 568 REJ09B0348-0100 Section 17 14-Bit PWM Section 17 14-Bit PWM This LSI has an on-chip 14-bit pulse width modulator (PWM) with two channels. Connecting the PWM to the low-pass filter enables the PWM to be used as a D/A converter. Standard PWM or pulse-division type PWM can be selected by software. Figure 17.1 shows a block diagram of the 14-bit PWM. 17.1 Features * Choice of four conversion periods A conversion period of 131,072/ with a minimum modulation width of 8/, a conversion period of 65,536/ with a minimum modulation width of 4/, a conversion period of 32,768/ with a minimum modulation width of 2/, or a conversion period of 16,384/ with a minimum modulation width of 1/, can be selected. * Pulse division method for less ripple * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 6.4, Module Standby Function.) * The standard PWM or pulse-division type PWM can be selected by software. PWDR /2 /4 /8 /16 PWM waveform generator PWCR PWM Pulse-division type waveform Standard waveform AEC [Legend] PWDR: PWCR: PWM data register PWM control register PWM waveform generator Figure 17.1 Block Diagram of 14-Bit PWM Rev. 1.00 Dec. 18, 2006 Page 379 of 568 REJ09B0348-0100 Internal data bus Section 17 14-Bit PWM 17.2 Input/Output Pins Table 17.1 shows the 14-bit PWM pin configuration. Table 17.1 Pin Configuration Name PWM1 output pin PWM2 output pin Abbreviation PWM1 PWM2 I/O Output Output Function Standard PWM/pulse-division type PWM waveform output (PWM1) Standard PWM/pulse-division type PWM waveform output (PWM2) 17.3 Register Descriptions The 14-bit PWM has the following registers. * * * * PWM1 control register (PWCR1) PWM1 data register (PWDR1) PWM2 control register (PWCR2) PWM2 data register (PWDR2) PWM Control Register (PWCR) 17.3.1 PWCR selects the input clocks and selects whether the standard PWM or pulse-division type PWM is used. Bit 7 to 3 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 2 PWCRm2 0 W PWM Output Waveform Select Selects whether the standard PWM waveform or pulsedivision type PWM waveform is output. 0: Pulse-division type PWM waveform is output 1: Standard PWM waveform is output Rev. 1.00 Dec. 18, 2006 Page 380 of 568 REJ09B0348-0100 Section 17 14-Bit PWM Bit 1 0 Bit Name PWCRm1 PWCRm0 Initial Value 0 0 R/W W W Description Clock Select 1 and 0 Select the clock supplied to the 14-bit PWM. These bits are write-only bits and always read as 1. 00: The input clock is /2 (t* = 2/) A conversion period is 16,384/, with a minimum modulation width of 1/ 01: The input clock is /4 (t* = 4/) A conversion period is 32,768/, with a minimum modulation width of 2/ 10: The input clock is /8 (t* = 8/) A conversion period is 65,536/, with a minimum modulation width of 4/ 11: The input clock is /16 (t* = 16/) A conversion period is 131,072/, with a minimum modulation width of 8/ Note: * t: Period of PWM clock input m = 2 or 1 17.3.2 PWM Data Register (PWDR) PWDR is a 14-bit write-only register. PWDR indicates high level width in one PWM waveform cycle when the pulse-division type PWM is selected. When data is written to the lower fourteen bits of PWDR, the contents are latched in the PWM waveform generator and the PWM waveform generation data is updated. PWDR is initialized to H'C000 and the read value is always H'FFF. Rev. 1.00 Dec. 18, 2006 Page 381 of 568 REJ09B0348-0100 Section 17 14-Bit PWM 17.4 17.4.1 Operation Setting for Pulse-Division Type PWM Operation Pulse-division type PWM is obtained by dividing the high and low periods of a normal PWM waveform into equal numbers of parts for alternate output. This methodology reduces the ripple generated when the PWM unit is used with a low-pass filter as a D/A converter. As an example of such operation, figure 17.2 shows the derivation of a waveform that corresponds to the normal PWM signal divided by four. A 14-bit PWM signal is divided into 64 pulses. One conversion period Normal PWM (1) (2) (3) (4) (5) (6) (7) (8) Pulse-division PWM (division by 4) (1) (5) (2) (6) (3) (7) (4) (8) Figure 17.2 Operation of Pulse-Division-Type PWM with Division by 4 17.4.2 How to Set Pulse-Division Type PWM When using the pulse-division type PWM, set the register in this sequence:. 1. Set the PWM1 or PWM2 bit in PMR9 (according to the PWM channel used) to 1 to set the P90/PWM1 and P91/PWM2 pins to function as a PWM pin. 2. Set PWCR to select one conversion period. 3. Set the output waveform data in PWDR. When the data is written to PWDR, the contents are latched in the PWM waveform generator, and the PWM waveform generation data is updated. Rev. 1.00 Dec. 18, 2006 Page 382 of 568 REJ09B0348-0100 Section 17 14-Bit PWM 17.4.3 Operation of Pulse-Division Type PWM One conversion period consists of 64 pulses, as shown in figure 17.3. The total high-level width during this period (TH) corresponds to the data in PWDR. This relation is shown in table 17.2. One conversion period tf1 tf2 tf63 tf64 tH1 tf1 = tf2 = tf3 t tH2 tH3 tH63 tH64 TH = tH1 + tH2 + tH3 + . . . tH64 . . . = H64 Figure 17.3 Waveform Output by PWM Table 17.2 Relation between PWCR and PWDR PWCRm Value PWCRm1 0 0 1 1 Note: m = 2, 1 0 1 0 1 PWCRm0 1 Conversion Time (tcyc) 16384 32768 65536 131072 TH (tcyc) (PWDRm + 64) x 1 (PWDRm + 64) x 2 (PWDRm + 64) x 4 (PWDRm + 64) x 8 256 512 1024 2048 tfn (n = 1 to 64) (tcyc) Rev. 1.00 Dec. 18, 2006 Page 383 of 568 REJ09B0348-0100 Section 17 14-Bit PWM 17.4.4 Setting for Standard PWM Operation When using the standard PWM, set the registers in this sequence: 1. Set the PWM1 or PWM2 bit in PMR9 (according to the PWM channel used) to 1 to set the P90/PWM1 or P91/PWM2 pin to function as a PWM pin. 2. Set PWCRm2 to 1 to select the standard PWM waveform. (m = 2 or 1) 3. Set the event counter PWM in the asynchronous event counter. For the setting method, see description of the event counter PWM operation in the asynchronous event counter. 4. The PWM pin outputs the PWM waveform set by the event counter. Note: When the standard waveform is used, 16-bit counter, 8-bit counter, and IRQAEC operation of the asynchronous event counter are not available because the asynchronous event counter is used for PWM. ECH and ECL are incremented while the IECPWM signal of the asynchronous event counter is at the high level but stop when it is at the low level (for details, refer to section 13.4, Operation). Rev. 1.00 Dec. 18, 2006 Page 384 of 568 REJ09B0348-0100 Section 17 14-Bit PWM 17.5 PWM Operating States The PWM operating states are shown in table 17.3. Table 17.3 PWM Operating States Operating Mode PWCRm PWDRm Reset Reset Reset Active Functions Functions Sleep Functions Functions Watch Retained Retained Subactive Subsleep Standby Functions* Retained Retained Retained Retained Retained Module Standby Retained Retained Note: * m = 2, 1 Writing is possible. 17.6 17.6.1 Usage Notes Relation between Writing to PWDR and Updating of PWM Waveform When the value in PWDR is changed during PWM waveform output, the operation is determined by the state of the waveform at the time of writing to PWDR. 1. When the low signal is being output, the waveform will be updated from the next pulse. 2. When a high level is being output, timing relations determine the behavior as listed below. a. If the new value increases the duty cycle, the waveform is updated immediately. b. If the new value decreases the duty cycle and the high period of a single pulse is greater than that defined by the new setting in PWDR, the output remains high for a single pulse period. c. If the new value decreases the duty cycle and the high period of a single pulse is less than or equal to that defined by the new setting in PWDR, the change is reflected in the waveform immediately after writing to PWDR. Rev. 1.00 Dec. 18, 2006 Page 385 of 568 REJ09B0348-0100 Section 17 14-Bit PWM Rev. 1.00 Dec. 18, 2006 Page 386 of 568 REJ09B0348-0100 Section 18 A/D Converter Section 18 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The block diagram of the A/D converter is shown in figure 18.1. 18.1 * * * * * Features 10-bit resolution Input channels: Eight channels High-speed conversion: 12.4 s per channel (at 5-MHz operation) Sample and hold function Conversion start method A/D conversion can be started by software and external trigger. * Interrupt source An A/D conversion end interrupt request can be generated. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 6.4, Module Standby Function.) Rev. 1.00 Dec. 18, 2006 Page 387 of 568 REJ09B0348-0100 Section 18 A/D Converter ADTRG AMR AN0 AN1 AN2 AN4 AN5 AN6 AN7 ADSR Multiplexer AVCC + Comparator Reference voltage AVSS Control logic AVCC AVSS ADRR [Legend] AMR: ADSR: ADRR: IRRAD: A/D mode register A/D start register A/D result register A/D conversion end interrupt request flag Internal data bus AN3 IRRAD Figure 18.1 Block Diagram of A/D Converter Rev. 1.00 Dec. 18, 2006 Page 388 of 568 REJ09B0348-0100 Section 18 A/D Converter 18.2 Input/Output Pins Table 18.1 shows the input pins used by the A/D converter. Table 18.1 Pin Configuration Pin Name Analog power supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 External trigger input pin Abbreviation AVcc AVss AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Function Power supply and reference voltage of analog part Ground and reference voltage of analog part Analog input pins External trigger input that controls the A/D conversion start. 18.3 Register Descriptions The A/D converter has the following registers. * A/D result register (ADRR) * A/D mode register (AMR) * A/D start register (ADSR) 18.3.1 A/D Result Register (ADRR) ADRR is a 16-bit read-only register that stores the results of A/D conversion. The upper 10 bits of the data are stored in ADRR. ADRR can be read by the CPU at any time, but the ADRR value during A/D conversion is undefined. After A/D conversion is completed, the conversion result is stored as 10-bit data, and this data is retained until the next conversion operation starts. The initial value of ADRR is undefined. Rev. 1.00 Dec. 18, 2006 Page 389 of 568 REJ09B0348-0100 Section 18 A/D Converter 18.3.2 A/D Mode Register (AMR) AMR sets the A/D conversion time, and selects the external trigger and analog input pins. Bit 7 Bit Name CKS Initial Value 0 R/W R/W Description Clock Select Selects the clock source for A/D conversion. 0: /4 (conversion time = 62 states (max.) (basic clock = 4)) 1: /2 (conversion time = 31 states (max.) (basic clock = 4)) 6 TRGE 0 R/W External Trigger Select Enables or disables the A/D conversion start by the external trigger input. 0: Disables the A/D conversion start by the external trigger input. 1: Starts A/D conversion at the rising or falling edge of the ADTRG pin The edge of the ADTRG pin is selected by the ADTRGNEG bit in IEGR. 5 4 3 2 1 0 CH3 CH2 CH1 CH0 1 1 0 0 0 0 R/W R/W R/W R/W Reserved These bits are always read as 1 and cannot be modified. Channel Select 3 to 0 Select the analog input channel. 00xx: No channel selected 0100: AN0 0101: AN1 0110: AN2 0111: AN3 1000: AN4 1001: AN5 1010: AN6 1011: AN7 11xx: Using prohibited The channel selection should be made while the ADSF bit is cleared to 0. [Legend] x: Don't care. Rev. 1.00 Dec. 18, 2006 Page 390 of 568 REJ09B0348-0100 Section 18 A/D Converter 18.3.3 A/D Start Register (ADSR) ADSR starts and stops the A/D conversion. Bit 7 Bit Name ADSF Initial Value 0 R/W R/W Description When this bit is set to 1, A/D conversion is started. When conversion is completed, the converted data is set in ADRR and at the same time this bit is cleared to 0. If this bit is written to 0, A/D conversion can be forcibly terminated. Reserved These bits are always read as 1 and cannot be modified. 6 to 0 All 1 18.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. When changing the conversion time or analog input channel, in order to prevent incorrect operation, first clear the bit ADSF to 0 in ADSR. 18.4.1 1. 2. 3. 4. A/D Conversion A/D conversion is started from the selected channel when the ADSF bit in ADSR is set to 1, according to software. When A/D conversion is completed, the result is transferred to the A/D result register. On completion of conversion, the IRRAD flag in IRR2 is set to 1. If the IENAD bit in IENR2 is set to 1 at this time, an A/D conversion end interrupt request is generated. The ADSF bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADSF bit is automatically cleared to 0 and the A/D converter enters the wait state. Rev. 1.00 Dec. 18, 2006 Page 391 of 568 REJ09B0348-0100 Section 18 A/D Converter 18.4.2 External Trigger Input Timing The A/D converter can also start A/D conversion by input of an external trigger signal. External trigger input is enabled at the ADTRG pin when the ADTSTCHG bit in PMRB is set to 1* and TRGE bit in AMR is set to 1. Then when the input signal edge designated in the ADTRGNEG bit in IEGR is detected at the ADTRG pin, the ADSF bit in ADSR will be set to 1, starting A/D conversion. Figure 18.2 shows the timing. Note: * The ADTRG input pin is shared with the TEST pin. Therefore when the pin is used as the ADTRG pin, reset should be cleared while the 0-fixed or 1-fixed signal is input to the TEST pin. Then the ADTSTCHG bit should be set to 1 after the TEST signal is fixed. ADTRG (when ADTRGNEG = 0) ADSF A/D conversion Figure 18.2 External Trigger Input Timing 18.4.3 Operating States of A/D Converter Table 18.2 shows the operating states of the A/D converter. Table 18.2 Operating States of A/D Converter Operating Mode AMR ADSR ADRR Reset Reset Reset Retained* Active Functions Functions Functions Sleep Functions Functions Functions Watch Retained Retained Retained Subactive Retained Retained Retained Subsleep Retained Retained Retained Standby Retained Retained Retained Module Standby Retained Retained Retained Note: * Undefined at a power-on reset. Rev. 1.00 Dec. 18, 2006 Page 392 of 568 REJ09B0348-0100 Section 18 A/D Converter 18.5 Example of Use An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as the analog input channel. Figure 18.3 shows the operation timing. 1. Bits CH3 to CH0 in the A/D mode register (AMR) are set to 0101, making pin AN1 the analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1. When A/D conversion is completed, bit IRRAD is set to 1, and the A/D conversion result is stored in ADRR. At the same time bit ADSF is cleared to 0, and the A/D converter goes to the idle state. Bit IENAD = 1, so an A/D conversion end interrupt is requested. The A/D interrupt handling routine starts. The A/D conversion result is read and processed. The A/D interrupt handling routine ends. 2. 3. 4. 5. 6. If bit ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. Figures 18.4 and 18.5 show flowcharts of procedures for using the A/D converter. Rev. 1.00 Dec. 18, 2006 Page 393 of 568 REJ09B0348-0100 REJ09B0348-0100 Set* Set* Set* Idle A/D conversion (1) Section 18 A/D Converter Interrupt (IRRAD) Rev. 1.00 Dec. 18, 2006 Page 394 of 568 Idle Read conversion result A/D conversion result (1) A/D conversion (2) IENAD ADSF A/D conversion starts Channel 1 (AN1) operating state Idle Read conversion result A/D conversion result (2) ADRR Figure 18.3 Example of A/D Conversion Operation Note: * indicates instruction execution by software. Section 18 A/D Converter Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR No ADSF = 0? Yes Read ADRR data Yes Perform A/D conversion? No End Figure 18.4 Flowchart of Procedure for Using A/D Converter (Polling by Software) Start Set A/D conversion speed and input channel Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt generated? No Yes Clear IRRAD bit in IRR2 to 0 Read ADRR data Yes Perform A/D conversion? No End Figure 18.5 Flowchart of Procedure for Using A/D Converter (Interrupts Used) Rev. 1.00 Dec. 18, 2006 Page 395 of 568 REJ09B0348-0100 Section 18 A/D Converter 18.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 18.6). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 18.7). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 18.7). * Nonlinearity error The error with respect to the ideal A/D conversion characteristics between zero voltage and full-scale voltage. Does not include offset error, full-scale error, or quantization error. * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error. Rev. 1.00 Dec. 18, 2006 Page 396 of 568 REJ09B0348-0100 Section 18 A/D Converter Digital output 111 110 101 100 011 010 001 000 1 8 Ideal A/D conversion characteristic Quantization error 2 8 3 8 4 8 5 8 6 8 7 FS 8 Analog input voltage Figure 18.6 A/D Conversion Accuracy Definitions (1) Digital output Full-scale error Ideal A/D conversion characterist Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 18.7 A/D Conversion Accuracy Definitions (2) Rev. 1.00 Dec. 18, 2006 Page 397 of 568 REJ09B0348-0100 Section 18 A/D Converter 18.7 18.7.1 Usage Notes Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and therefore the level of the signal source impedance does not need to be taken into consideration. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 18.8). When converting a high-speed analog signal, a low-impedance buffer should be inserted. 18.7.2 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND. Care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board. This LSI Sensor output impedance up to 10 k Sensor input Low-pass filter C up to 0.1 F Cin = 15 pF A/D converter equivalent circuit 10 k 48 pF Figure 18.8 Example of Analog Input Circuit Rev. 1.00 Dec. 18, 2006 Page 398 of 568 REJ09B0348-0100 Section 18 A/D Converter 18.7.3 1. 2. 3. 4. Usage Notes ADRR should be read only when the ADSF bit in ADSR is cleared to 0. Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy. When A/D conversion is started after clearing module standby mode, wait for 10 clock cycles before starting A/D conversion. In active mode and sleep mode, the analog power supply current flows in the ladder resistance even when the A/D converter is on standby. Therefore, if the A/D converter is not used, it is recommended that AVcc be connected to the system power supply and the ADCKSTP bit be cleared to 0 in CKSTPR1. Rev. 1.00 Dec. 18, 2006 Page 399 of 568 REJ09B0348-0100 Section 18 A/D Converter Rev. 1.00 Dec. 18, 2006 Page 400 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Section 19 I2C Bus Interface 2 (IIC2) The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 19.1 shows a block diagram of the I2C bus interface 2. Figure 19.2 shows an example of I/O pin connections to external circuits. 19.1 Features * Selection of I2C format or clock synchronous serial format * Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 6.4, Module Standby Function.) I2C bus format Start and stop conditions generated automatically in master mode Selection of acknowledge output levels when receiving Automatic loading of acknowledge bit when transmitting Bit synchronization/wait function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission/reception is not yet possible, set the SCL to low until preparations are completed. * Six interrupt sources Transmit data empty (including slave-address match), transmit end, receive data full (including slave-address match), arbitration lost, NACK detection, and stop condition detection * Direct bus drive Two pins, SCL and SDA pins, function as CMOS outputs in normal operation (when the port/serial function is selected) and NMOS outputs when the bus drive function is selected. Clock synchronous format * Four interrupt sources Transmit-data-empty, transmit-end, receive-data-full, and overrun error * * * * Rev. 1.00 Dec. 18, 2006 Page 401 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Transfer clock generation circuit SCL Output control Transmission/ reception control circuit ICCR1 ICCR2 ICMR Noise canceler ICDRT SAR SDA Output control ICDRS Noise canceler Address comparator ICDRR Bus state decision circuit Arbitration decision circuit ICSR ICIER Interrupt generator [Legend] ICCR1: ICCR2: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: I2C bus control register 1 I2C bus control register 2 I2C bus mode register I2C bus status register I2C bus interrupt enable register I2C bus transmit data register I2C bus receive data register I2C bus shift register Slave address register Figure 19.1 Block Diagram of I2C Bus Interface 2 Rev. 1.00 Dec. 18, 2006 Page 402 of 568 REJ09B0348-0100 Internal data bus Interrupt request Section 19 I C Bus Interface 2 (IIC2) 2 Vcc SCL Vcc SCL SCL in SCL out SDA in SDA out (Master) SDA SDA SCL SDA SCL in SCL out SCL in SCL out SDA in SDA out (Slave 1) SDA in SDA out (Slave 2) Figure 19.2 External Circuit Connections of I/O Pins 19.2 Input/Output Pins Table 19.1 summarizes the input/output pins used by the I2C bus interface 2. Table 19.1 Pin Configuration Name Serial clock pin Serial data pin Abbreviation SCL SDA I/O I/O I/O Function IIC serial clock input/output IIC serial data input/output Rev. 1.00 Dec. 18, 2006 Page 403 of 568 REJ09B0348-0100 SCL SDA Section 19 I C Bus Interface 2 (IIC2) 2 19.3 Register Descriptions The I2C bus interface 2 has the following registers. * * * * * * * * * I2C bus control register 1 (ICCR1) I2C bus control register 2 (ICCR2) I2C bus mode register (ICMR) I2C bus interrupt enable register (ICIER) I2C bus status register (ICSR) Slave address register (SAR) I2C bus transmit data register (ICDRT) I2C bus receive data register (ICDRR) I2C bus shift register (ICDRS) I2C Bus Control Register 1 (ICCR1) 19.3.1 ICCR1 enables or disables the I2C bus interface 2, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit 7 Bit Name ICE Initial Value 0 R/W R/W Description I2C Bus Interface Enable 0: This module is halted. (SCL and SDA pins are set to the port/serial function.) 1: This bit is enabled for transfer operations. (SCL and SDA pins are bus drive state.) 6 RCVD 0 R/W Reception Disable This bit enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception Rev. 1.00 Dec. 18, 2006 Page 404 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Bit 5 4 Bit Name MST TRS Initial Value 0 0 R/W R/W R/W Description Master/Slave Select Transmit/Receive Select In master mode with the I2C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. After data receive has been started in slave receive mode, when the first seven bits of the receive data agree with the slave address that is set to SAR and the eighth bit is 1, TRS is automatically set to 1. If an overrun error occurs in master mode with the clock synchronous serial format, MST is cleared to 0 and slave receive mode is entered. Operating modes are described below according to MST and TRS combination. When clock synchronous serial format is selected and MST is 1, clock is output. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode 3 2 1 0 CKS3 CKS2 CKS1 CKS0 0 0 0 0 R/W R/W R/W R/W Transfer Clock Select 3 to 0 In master mode, set these bits according to the necessary transfer rate (see table 19.2, Transfer Rate). In slave mode, these bits are used to secure the data setup time in transmission mode. When CKS3 = 0, the data setup time is 10 tcyc and when CKS3 = 1, the data setup time is 20 tcyc. Rev. 1.00 Dec. 18, 2006 Page 405 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Table 19.2 Transfer Rate Bit 3 CKS3 0 Bit 2 CKS2 0 Bit 1 CKS1 0 1 1 0 1 1 0 0 1 1 0 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 = 2 MHz Transfer Rate = 5 MHz = 10 MHz 71.4 kHz 50.0 kHz 41.7 kHz 31.3 kHz 25.0 kHz 20.0 kHz 17.9 kHz 15.6 kHz 35.7 kHz 25.0 kHz 20.8 kHz 15.6 kHz 12.5 kHz 10.0 kHz 8.9 kHz 7.8 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz Rev. 1.00 Dec. 18, 2006 Page 406 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 19.3.2 I2C Bus Control Register 2 (ICCR2) ICCR1 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus interface 2. Bit 7 Bit Name BBSY Initial Value 0 R/W R/W Description Bus Busy This bit enables to confirm whether the I2C bus is occupied or released and to issue start/stop conditions in master mode. With the clock synchronous serial format, this bit has no meaning. With the I2C bus format, this bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. Write 1 to BBSY and 0 to SCP to issue a start condition. Follow this procedure when also re-transmitting a start condition. Write 0 in BBSY and 0 in SCP to issue a stop condition. To issue start/stop conditions, use the MOV instruction. 6 SCP 1 R/W Start/Stop Issue Condition Disable The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. 5 SDAO 1 R/W SDA Output Value Control This bit is used with SDAOP when modifying output level of SDA. This bit should not be manipulated during transfer. 0: When reading, SDA pin outputs low. When writing, SDA pin is changed to output low. 1: When reading, SDA pin outputs high. When writing, SDA pin is changed to output Hi-Z (outputs high by external pull-up resistance). Rev. 1.00 Dec. 18, 2006 Page 407 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Bit 4 Bit Name SDAOP Initial Value 1 R/W R/W Description SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1. 3 SCLO 1 R This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low. Reserved This bit is always read as 1, and cannot be modified. IIC Control Part Reset This bit resets the control part except for I2C registers. If this bit is set to 1 when hang-up occurs because of communication failure during I2C operation, I2C control part can be reset without setting ports and initializing registers. 2 1 IICRST 1 0 R/W 0 1 Reserved This bit is always read as 1, and cannot be modified. Rev. 1.00 Dec. 18, 2006 Page 408 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 19.3.3 I2C Bus Mode Register (ICMR) ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count. Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I2C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit In master mode with the I2C bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The setting of this bit is invalid in slave mode with the I2C bus format or with the clock synchronous serial format. 5, 4 All 1 Reserved These bits are always read as 1, and cannot be modified. 3 BCWP 1 R/W BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0 and use the MOV instruction. In clock synchronous serial mode, BC should not be modified. 0: When writing, values of BC2 to BC0 are set. 1: When reading, 1 is always read. When writing, settings of BC2 to BC0 are invalid. Rev. 1.00 Dec. 18, 2006 Page 409 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Bit 2 1 0 Bit Name BC2 BC1 BC0 Initial Value 0 0 0 R/W R/W R/W R/W Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. With the I2C bus format, the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL pin is low. The value returns to 000 at the end of a data transfer, including the acknowledge bit. With the clock synchronous serial format, these bits should not be modified. I2C Bus Format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits Clock Synchronous Serial Format 000: 8 bits 001: 1 bits 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits Rev. 1.00 Dec. 18, 2006 Page 410 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 19.3.4 I2C Bus Interrupt Enable Register (ICIER) ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled. 1: Transmit data empty interrupt request (TXI) is enabled. 6 TEIE 0 R/W Transmit End Interrupt Enable This bit enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled. 1: Transmit end interrupt request (TEI) is enabled. 5 RIE 0 R/W Receive Interrupt Enable This bit enables or disables the receive data full interrupt request (RXI) and the overrun error interrupt request (ERI) with the clock synchronous format, when a receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt request (RXI) and overrun error interrupt request (ERI) with the clock synchronous format are disabled. 1: Receive data full interrupt request (RXI) and overrun error interrupt request (ERI) with the clock synchronous format are enabled. Rev. 1.00 Dec. 18, 2006 Page 411 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Bit 4 Bit Name NAKIE Initial Value 0 R/W R/W Description NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clock synchronous format, when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled. 3 STIE 0 R/W Stop Condition Detection Interrupt Enable 0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled. 2 ACKE 0 R/W Acknowledge Bit Judgment Select 0: The value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: If the receive acknowledge bit is 1, continuous transfer is halted. 1 ACKBR 0 R Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. 0: Receive acknowledge = 0 1: Receive acknowledge = 1 0 ACKBT 0 R/W Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing. Rev. 1.00 Dec. 18, 2006 Page 412 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 19.3.5 I2C Bus Status Register (ICSR) ICSR performs confirmation of interrupt request flags and status. Bit 7 Bit Name TDRE Initial Value 0 R/W R/W Description Transmit Data Register Empty [Setting condition] * * * * When data is transferred from ICDRT to ICDRS and ICDRT becomes empty When TRS is set When a start condition (including re-transfer) has been issued When transmit mode is entered from receive mode in slave mode When 0 is written in TDRE after reading TDRE = 1 When data is written to ICDRT with an instruction [Clearing conditions] * * 6 TEND 0 R/W Transmit End [Setting conditions] * * When the ninth clock of SCL rises with the I C bus format while the TDRE flag is 1 When the final bit of transmit frame is sent with the clock synchronous serial format When 0 is written in TEND after reading TEND = 1 When data is written to ICDRT with an instruction 2 [Clearing conditions] * * 5 RDRF 0 R/W Receive Data Register Full [Setting condition] * When a receive data is transferred from ICDRS to ICDRR When 0 is written in RDRF after reading RDRF = 1 When ICDRR is read with an instruction [Clearing conditions] * * Rev. 1.00 Dec. 18, 2006 Page 413 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Bit 4 Bit Name NACKF Initial Value 0 R/W R/W Description No Acknowledge Detection Flag [Setting condition] * When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 When 0 is written in NACKF after reading NACKF = 1 [Clearing condition] * 3 STOP 0 R/W Stop Condition Detection Flag [Setting condition] * When a stop condition is detected after frame transfer When 0 is written in STOP after reading STOP = 1 [Clearing condition] * 2 AL/OVE 0 R/W Arbitration Lost Flag/Overrun Error Flag This flag indicates that arbitration was lost in master 2 mode with the I C bus format and that the final bit has been received while RDRF = 1 with the clock synchronous format. When two or more master devices attempt to seize the 2 bus at nearly the same time, if the I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. [Setting conditions] * * * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode When the SDA pin outputs high in master mode while a start condition is detected When the final bit is received with the clock synchronous format while RDRF = 1 When 0 is written in AL/OVE after reading AL/OVE=1 [Clearing condition] * Rev. 1.00 Dec. 18, 2006 Page 414 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Bit 1 Bit Name AAS Initial Value 0 R/W R/W Description Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] * * When the slave address is detected in slave receive mode When the general call address is detected in slave receive mode. When 0 is written in AAS after reading AAS=1 2 [Clearing condition] * 0 ADZ 0 R/W General Call Address Recognition Flag This bit is valid in I C bus format slave receive mode. [Setting condition] * When the general call address is detected in slave receive mode When 0 is written in ADZ after reading ADZ=1 [Clearing conditions] * 19.3.6 Slave Address Register (SAR) SAR selects the communication format and sets the slave address. When the chip is in slave mode with the I2C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device. Bit 7 to 1 Bit Name SVA6 to SVA0 Initial Value All 0 R/W R/W Description Slave Address 6 to 0 These bits set a unique address in bits SVA6 to SVA0, differing form the addresses of other slave devices 2 connected to the I C bus. 0 R/W Format Select 0: I C bus format is selected. 1: Clock synchronous serial format is selected. 2 0 FS Rev. 1.00 Dec. 18, 2006 Page 415 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 19.3.7 I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1 and when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of ICDRT is H'FF. The initial value of ICDRT is H'FF. 19.3.8 I2C Bus Receive Data Register (ICDRR) ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR is H'FF. 19.3.9 I2C Bus Shift Register (ICDRS) ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the CPU. Rev. 1.00 Dec. 18, 2006 Page 416 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 19.4 Operation The I2C bus interface can communicate either in I2C bus mode or clock synchronous serial mode by setting FS in SAR. 19.4.1 I2C Bus Format Figure 19.3 shows the I2C bus formats. Figure 19.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits. (a) I2C bus format (FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: Transfer bit count (n = 1 to 8) m: Transfer frame count (m 1) (b) I2C bus format (Start condition retransmission, FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1 1 n1 and n2: Transfer bit count (n1 and n2 = 1 to 8) m1 and m2: Transfer frame count (m1 and m2 1) Figure 19.3 I2C Bus Formats SDA SCL S 1 to 7 SLA 8 R/W 9 A 1 to 7 DATA 8 9 A 1 to 7 DATA 8 9 A P Figure 19.4 I2C Bus Timing Rev. 1.00 Dec. 18, 2006 Page 417 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 [Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high. 19.4.2 Master Transmit Operation In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For master transmit mode operation timing, refer to figures 19.5 and 19.6. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Read the BBSY flag in ICCR2 to confirm that the bus is free. Set the MST and TRS bits in ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV instruction. (Start condition issued) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0, and data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop condition. To issue the stop condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode. Rev. 1.00 Dec. 18, 2006 Page 418 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 SCL (Master output) SDA (Master output) 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W 9 1 Bit 7 2 Bit 6 Slave address SDA (Slave output) TDRE TEND ICDRT ICDRS Address + R/W A Data 1 Data 2 Address + R/W Data 1 User processing [2] Instruction of start condition issuance [4] Write data to ICDRT (second byte) [3] Write data to ICDRT (first byte) [5] Write data to ICDRT (third byte) Figure 19.5 Master Transmit Mode Operation Timing (1) SCL (Master output) SDA (Master output) SDA (Slave output) 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 9 A A/A TDRE TEND ICDRT ICDRS Data n Data n User [5] Write data to ICDRT processing [6] Issue stop condition. Clear TEND. [7] Set slave receive mode Figure 19.6 Master Transmit Mode Operation Timing (2) Rev. 1.00 Dec. 18, 2006 Page 419 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 19.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 19.7 and 19.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0 and set the ACKBT bit in ICIER. 2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. The master device outputs the level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse. 3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF is cleared to 0. 4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is fixed low until ICDRR is read. 5. If next frame is the last receive data, set the RCVD bit in ICCR1 and set the ACKBT bit in ICIER. to 1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, and clearing the STOP bit in ICSR issue the stage condition. 7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0. 8. Clear the MST bit in ICCR1 and then, the operation returns to the slave receive mode. Rev. 1.00 Dec. 18, 2006 Page 420 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Master transmit mode SCL (Master output) SDA (Master output) SDA (Slave output) TDRE TEND TRS RDRF ICDRS ICDRR User processing A 9 1 Master receive mode 2 3 4 5 6 7 8 9 A 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Data 1 Data 1 [3] Read ICDRR [1] Clear TDRE after clearing [2] Read ICDRR (dummy read) TEND and TRS Figure 19.7 Master Receive Mode Operation Timing (1) Rev. 1.00 Dec. 18, 2006 Page 421 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 SCL (Master output) SDA (Master output) SDA (Slave output) 9 A 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS ICDRR User processing Data n-1 Data n-1 Data n Data n [5] Read ICDRR after setting RCVD [7] Read ICDRR, and clear RCVD [6] Issue stop condition [8] Set slave receive mode Figure 19.8 Master Receive Mode Operation Timing (2) Rev. 1.00 Dec. 18, 2006 Page 422 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 19.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, refer to figures 19.9 and 19.10. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by writing transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free. 5. Clear TDRE. Rev. 1.00 Dec. 18, 2006 Page 423 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Slave receive mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) Slave transmit mode 9 1 2 3 4 5 6 7 8 9 A 1 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS ICDRT Data 1 Data 2 Data 3 ICDRS ICDRR User processing Data 1 Data 2 [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3) Figure 19.9 Slave Transmit Mode Operation Timing (1) Rev. 1.00 Dec. 18, 2006 Page 424 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Slave receive mode Slave transmit mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 A 1 2 3 4 5 6 7 8 9 A TDRE TEND TRS ICDRT ICDRS ICDRR User processing Data n [3] Clear TEND [4] Read ICDRR (dummy read) [5] Clear TDRE after clearing TRS Figure 19.10 Slave Transmit Mode Operation Timing (2) 19.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, refer to figures 19.11 and 19.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the read data show the slave address and R/W, it is not used.) Rev. 1.00 Dec. 18, 2006 Page 425 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR. SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 9 1 Bit 7 A A RDRF ICDRS ICDRR User processing Data 1 Data 2 Data 1 [2] Read ICDRR (dummy read) [2] Read ICDRR Figure 19.11 Slave Receive Mode Operation Timing (1) SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) RDRF ICDRS ICDRR User processing A A 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 9 Data 1 Data 2 Data 1 [3] Set ACKBT [3] Read ICDRR [4] Read ICDRR Figure 19.12 Slave Receive Mode Operation Timing (2) Rev. 1.00 Dec. 18, 2006 Page 426 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 19.4.6 Clock Synchronous Serial Format This module can be operated with the clock synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. (1) Data Transfer Format Figure 19.13 shows the clock synchronous serial transfer format. The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the SDAO bit in ICCR2. SCL SDA Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 19.13 Clock Synchronous Serial Transfer Format Rev. 1.00 Dec. 18, 2006 Page 427 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 (2) Transmit Operation In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, refer to figure 19.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set. 3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous transmission is performed by writing data to ICDRT every time TDRE is set. When changing from transmit mode to receive mode, clear TRS while TDRE is 1. SCL SDA (Output) 1 Bit 0 2 Bit 1 7 Bit 6 8 Bit 7 1 Bit 0 7 Bit 6 8 Bit 7 1 Bit 0 TRS TDRE ICDRT ICDRS User processing Data 1 Data 1 Data 2 Data 2 Data 3 Data 3 [3] Write data [3] Write data to ICDRT to ICDRT [2] Set TRS [3] Write data to ICDRT [3] Write data to ICDRT Figure 19.14 Transmit Mode Operation Timing Rev. 1.00 Dec. 18, 2006 Page 428 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 (3) Receive Operation In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to figure 19.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. When the transfer clock is output, set MST to 1 to start outputting the receive clock. 3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is continually output. The continuous reception is performed by reading ICDRR every time RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR. 4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is fixed high after receiving the next byte data. SCL SDA (Input) MST TRS RDRF ICDRS ICDRR User processing 1 Bit 0 2 Bit 1 7 Bit 6 8 Bit 7 1 Bit 0 7 Bit 6 8 Bit 7 1 Bit 0 2 Bit 1 Data 1 Data 2 Data 1 Data 3 Data 2 [2] Set MST (when outputting the clock) [3] Read ICDRR [3] Read ICDRR Figure 19.15 Receive Mode Operation Timing Rev. 1.00 Dec. 18, 2006 Page 429 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 19.4.7 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 19.16 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock C SCL or SDA input signal D Latch Q D C Q Latch Match detector Internal SCL or SDA signal System clock period Sampling clock Figure 19.16 Block Diagram of Noise Conceler 19.4.8 Example of Use Flowcharts in respective modes that use the I2C bus interface are shown in figures 19.17 to 19.20. Rev. 1.00 Dec. 18, 2006 Page 430 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Start Initialize Read BBSY in ICCR2 [1] [2] Test the status of the SCL and SDA lines. Set master transmit mode. Issue the start candition. Set the first byte (slave address + R/W) of transmit data. Wait for 1 byte to be transmitted. Test the acknowledge transferred from the specified slave device. Set the second and subsequent bytes (except for the final byte) of transmit data. Wait for ICDRT empty. Set the last byte of transmit data. No [1] BBSY=0 ? Yes Set MST and TRS in ICCR1 to 1. Write 1 to BBSY and 0 to SCP. Write transmit data in ICDRT Read TEND in ICSR [3] [2] [3] [4] [4] [5] [6] [7] No [5] TEND=1 ? Yes Read ACKBR in ICIER [6] ACKBR=0 ? Yes Transmit mode? Yes No [8] [9] [10] Wait for last byte to be transmitted. [11] Clear the TEND flag. No Mater receive mode [12] Clear the STOP flag. [13] Issue the stop condition. Write transmit data in ICDRT Read TDRE in ICSR No [7] [8] TDRE=1 ? Yes [14] Wait for the creation of stop condition. [15] Set slave receive mode. Clear TDRE. No Last byte? [9] Yes Write transmit data in ICDRT Read TEND in ICSR No [10] TEND=1 ? Yes Clear TEND in ICSR Clear STOP in ICSR [11] [12] Write 0 to BBSY and SCP Read STOP in ICSR No [13] [14] STOP=1 ? Yes Set MST to 1 and TRS to 0 in ICCR1 [15] Clear TDRE in ICSR End Figure 19.17 Sample Flowchart for Master Transmit Mode Rev. 1.00 Dec. 18, 2006 Page 431 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* Set acknowledge to the transmit device.* Dummy-read ICDRR.* Wait for 1 byte to be received Check whether it is the (last receive - 1). Read the receive data. Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). Read the (final byte - 1) of receive data. Wait for the last byte to be receive. Clear TEND in ICSR Clear TRS in ICCR1 to 0 Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR No [2] [2] [1] [3] [4] [5] [6] [7] [8] [3] RDRF=1 ? Yes [4] Last receive - 1? No Read ICDRR Yes [5] [9] [10] Clear the STOP flag. [6] [11] Issue the stop condition. [12] Wait for the creation of stop condition. Set ACKBT in ICIER to 1 [7] [13] Read the last byte of receive data. [14] Clear RCVD. Set RCVD in ICCR1 to 1 Read ICDRR Read RDRF in ICSR [8] [15] Set slave receive mode. No RDRF=1 ? Yes Clear STOP in ICSR. [9] [10] Write 0 to BBSY and SCP Read STOP in ICSR No [11] [12] STOP=1 ? Yes Read ICDRR Clear RCVD in ICCR1 to 0 [13] [14] Clear MST in ICCR1 to 0 End [15] Note: When 1 byte is received, skip steps [2] to [6] after [1] and then jump to step [7]. In step [8], dummy-read ICDRR. * Do not activate an interrupt during the execution of steps [1] to [3]. Figure 19.18 Sample Flowchart for Master Receive Mode Rev. 1.00 Dec. 18, 2006 Page 432 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR No [3] TDRE=1 ? Yes No Last byte? [1] Clear the AAS flag. [1] [2] Set transmit data for ICDRT (except for the last data). [3] Wait for ICDRT empty. [2] [4] Set the last byte of transmit data. [5] Wait for the last byte to be transmitted. [6] Clear the TEND flag . [7] Set slave receive mode. [8] Dummy-read ICDRR to release the SCL line. [4] [9] Clear the TDRE flag. Yes Write transmit data in ICDRT Read TEND in ICSR No [5] TEND=1 ? Yes Clear TEND in ICSR Clear TRS in ICCR1 to 0 Dummy read ICDRR Clear TDRE in ICSR End [6] [7] [8] [9] Figure 19.19 Sample Flowchart for Slave Transmit Mode Rev. 1.00 Dec. 18, 2006 Page 433 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR [1] [2] Set acknowledge to the transmit device. [2] [3] Dummy-read ICDRR. [3] [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1). [4] [6] Read the receive data. [7] Set acknowledge of the last byte. Read RDRF in ICSR No RDRF=1 ? Yes Last receive - 1? Yes [5] [8] Read the (last byte - 1) of receive data. [9] Wait the last byte to be received. No Read ICDRR [6] [10] Read for the last byte of receive data. Set ACKBT in ICIER to 1 [7] Read ICDRR Read RDRF in ICSR No [8] [9] RDRF=1 ? Yes Read ICDRR End [10] Note: When 1 byte is received, skip steps [2] to [6] after [1] and then jump to step [7]. In step [8], dummy-read ICDRR. Figure 19.20 Sample Flowchart for Slave Receive Mode Rev. 1.00 Dec. 18, 2006 Page 434 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 19.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun. Table 19.3 shows the contents of each interrupt request. Table 19.3 Interrupt Requests Clock SynchronI2C Mode ous Mode Interrupt Request Transmit Data Empty Transmit End Receive Data Full STOP Recognition NACK Receive Arbitration Lost/Overrun Abbreviation TXI TEI RXI STPI NAKI Interrupt Condition (TDRE=1) * (TIE=1) (TEND=1) * (TEIE=1) (RDRF=1) * (RIE=1) (STOP=1) * (STIE=1) {(NACKF=1)+(AL=1)} * (NAKIE=1) x x When interrupt conditions described in table 19.3 are 1 and the I bit in CCR is 0, the CPU executes interrupt exception processing. Interrupt sources should be cleared in the exception processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive data of one byte may be transmitted. Rev. 1.00 Dec. 18, 2006 Page 435 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 19.6 Bit Synchronous Circuit In master mode,this module has a possibility that high level period may be short in the two states described below. * When SCL is driven to low by the slave device * When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 19.21 shows the timing of the bit synchronous circuit and table 19.4 shows the time when SCL output changes from low to Hi-Z then SCL is monitored. SCL monitor timing reference clock SCL VIH Internal SCL Figure 19.21 Timing of Bit Synchronous Circuit Table 19.4 Time for Monitoring SCL CKS3 0 CKS2 0 1 1 0 1 Time for Monitoring SCL 7.5 tcyc 19.5 tcyc 17.5 tcyc 41.5 tcyc Rev. 1.00 Dec. 18, 2006 Page 436 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 19.7 Usage Notes 1. Confirm the ninth falling edge of the clock before issuing a stop or a repeated start condition. The ninth falling edge can be confirmed by monitoring the SCLO bit in the I2C bus control register B (ICCRB). If a stop or a repeated start condition is issued at certain timing in either of the following cases, the stop or repeated start condition may be issued incorrectly. The rising time of the SCL signal exceeds the time given in section 19.6, Bit Synchronous Circuit, because of the load on the SCL bus (load capacitance or pull-up resistance). The bit synchronous circuit is activated because a slave device holds the SCL bus low during the eighth clock. 2. The WAIT bit in the I2C bus mode register (ICMR) must be held 0. If the WAIT bit is set to 1, when a slave device holds the SCL signal low more than one transfer clock cycle during the eighth clock, the high level period of the ninth clock may be shorter than a given period. Rev. 1.00 Dec. 18, 2006 Page 437 of 568 REJ09B0348-0100 Section 19 I C Bus Interface 2 (IIC2) 2 Rev. 1.00 Dec. 18, 2006 Page 438 of 568 REJ09B0348-0100 Section 20 Power-On Reset Circuit Section 20 Power-On Reset Circuit This LSI has an on-chip power-on reset circuit. A block diagram of the power-on reset circuit is shown in figure 20.1. 20.1 Feature * Power-on reset circuit An internal reset signal is generated at turning the power on by externally connecting a capacitor. Vcc (Recommended) RES R (100 k) System clock 3-bit counter Internal reset signal CRES Voltage detector Figure 20.1 Power-On Reset Circuit Rev. 1.00 Dec. 18, 2006 Page 439 of 568 REJ09B0348-0100 Section 20 Power-On Reset Circuit 20.2 20.2.1 Operation Power-On Reset Circuit The operation timing of the power-on reset circuit is shown in figure 20.2. As the power supply voltage rises, the capacitor, which is externally connected to the RES pin, is gradually charged through the on-chip pull-up resistor (100 k). The low level of the RES pin is sent to the chip and the whole chip is reset. When the level of the RES pin reaches to the predetermined level, a voltage detection circuit detects it. Then a 3-bit counter starts counting up. When the 3-bit counter counts for 8 times, an overflow signal is generated and an internal reset signal is cleared. The capacitance (CRES) which is connected to the RES pin can be computed using the following formula; where the power supply rising time (t_vtr) is 5 ms, the RES rising time (t_vtr x 2) is 10 ms, and the on-chip resistor is 100 k. For details, see section 23, Electrical Characteristics. C= 10 ms 100 k = 0.01 F Note: Adjust the capacitance connected to the RES pin so that t_vtr x 2 exceeds the oscillation stabilization time. Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a power-on reset may not occur. Rev. 1.00 Dec. 18, 2006 Page 440 of 568 REJ09B0348-0100 Section 20 Power-On Reset Circuit t_vtr Vcc t_vtr x 2 RES V_rst Internal reset signal t_cr t_out (eight states) Figure 20.2 Power-On Reset Circuit Operation Timing Rev. 1.00 Dec. 18, 2006 Page 441 of 568 REJ09B0348-0100 Section 20 Power-On Reset Circuit Rev. 1.00 Dec. 18, 2006 Page 442 of 568 REJ09B0348-0100 Section 21 Address Break Section 21 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit in CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address. With the address break function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 6.4, Module Standby Function.) Figure 21.1 shows a block diagram of the address break. Internal address bus Comparator BAR2H Interrupt generation control circuit BDR2H BAR2L ABRKCR2 ABRKSR2 BDR2L Comparator Interrupt [Legend] BAR2H, BAR2L: BDR2H, BDR2L: ABRKCR2: ABRKSR2: Break address register 2 Break data register 2 Address break control register 2 Address break status register 2 Figure 21.1 Block Diagram of Address Break Rev. 1.00 Dec. 18, 2006 Page 443 of 568 REJ09B0348-0100 Internal data bus Section 21 Address Break 21.1 Register Descriptions The address break has the following registers. * * * * Address break control register 2 (ABRKCR2) Address break status register 2 (ABRKSR2) Break address register 2 (BAR2H, BAR2L) Break data register 2 (BDR2H, BDR2L) Address Break Control Register 2 (ABRKCR2) 21.1.1 ABRKCR2 sets address break conditions. Bit 7 Bit Name RTINTE2 Initial Value 1 R/W R/W Description RTE Interrupt Enable When this bit is 0, the interrupt immediately after executing RTE is masked and then one instruction must be executed. When this bit is 1, the interrupt is not masked. 6 5 CSEL21 CSEL20 0 0 R/W R/W Condition Select 1 and 0 These bits set address break conditions. 00: Instruction execution cycle (no data comparison) 01: CPU data read cycle 10: CPU data write cycle 11: CPU data read/write cycle 4 3 2 ACMP22 ACMP21 ACMP20 0 0 0 R/W R/W R/W Address Compare Condition Select 2 to 0 These bits set the comparison condition between the address set in BAR2 and the internal address bus. 000: Compares 16-bit addresses 001: Compares upper 12-bit addresses 010: Compares upper 8-bit addresses 011: Compares upper 4-bit addresses 1xx: Setting prohibited Rev. 1.00 Dec. 18, 2006 Page 444 of 568 REJ09B0348-0100 Section 21 Address Break Bit 1 0 Bit Name DCMP21 DCMP20 Initial Value 0 0 R/W R/W R/W Description Data Compare Condition Select 1 and 0 These bits set the comparison condition between the data set in BDR2 and the internal data bus. 00: No data comparison 01: Compares lower 8-bit data between BDR2L and data bus 10: Compares upper 8-bit data between BDR2H and data bus 11: Compares 16-bit data between BDR2 and data bus [Legend] x: Don't care. When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 21.1 shows the access and data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. For details on data widths of each register, see section 22.1, Register Addresses (Address Order). Table 21.1 Access and Data Bus Used Word Access Even Address ROM space RAM space I/O register with 8-bit data bus width I/O register with 16-bit data bus width*1 I/O register with 16-bit data bus width*2 Upper 8 bits Upper 8 bits Upper 8 bits Upper 8 bits Upper 8 bits Odd Address Lower 8 bits Lower 8 bits Upper 8 bits Lower 8 bits Lower 8 bits Byte Access Even Address Upper 8 bits Upper 8 bits Upper 8 bits -- Upper 8 bits Odd Address Upper 8 bits Upper 8 bits Upper 8 bits -- Upper 8 bits Notes: 1. Registers whose addresses do not range from H'FF96 and H'FF97, and H'FFB8 to H'FFBB with 16-bit data bus width. 2. Registers whose addresses range from H'FF96 and H'FF97, and H'FFB8 to H'FFBB. Rev. 1.00 Dec. 18, 2006 Page 445 of 568 REJ09B0348-0100 Section 21 Address Break 21.1.2 Address Break Status Register 2 (ABRKSR2) ABRKSR2 consists of the address break interrupt flag and the address break interrupt enable bit. Bit 7 Bit Name ABIF2 Initial Value 0 R/W R/W Description Address Break Interrupt Flag [Setting condition] When the condition set in ABRKCR2 is satisfied [Clearing condition] When 0 is written after ABIF=1 is read 6 ABIE2 0 R/W Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled. 5 to 0 -- All 1 -- Reserved These bits are always read as 1. 21.1.3 Break Address Registers 2 (BAR2H, BAR2L) BAR2H and BAR2L are 16-bit read/write registers that set the address for generating an address break interrupt. When setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. The initial value of this register is H'FFFF. 21.1.4 Break Data Registers 2 (BDR2H, BDR2L) BDR2H and BDR2L are 16-bit read/write registers that set the data for generating an address break interrupt. BDR2H is compared with the upper 8-bit data bus. BDR2L is compared with the lower 8-bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for even and odd addresses in the data transmission. Therefore, comparison data must be set in BDR2H for byte access. For word access, the data bus used depends on the address. See section 21.1.1, Address Break Control Register 2 (ABRKCR2), for details. The initial value of this register is undefined. Rev. 1.00 Dec. 18, 2006 Page 446 of 568 REJ09B0348-0100 Section 21 Address Break 21.2 Operation When the ABIF2 and ABIE2 bits in ABRKSR2 are set to 1, the address break function generates an interrupt request to the CPU. The ABIF2 bit in ABRKSR2 is set to 1 by the combination of the address set in BAR2, the data set in BDR2, and the conditions set in ABRKCR2. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked by the I bit in CCR of the CPU. Figures 21.2 show the operation examples of the address break interrupt setting. When the address break is specified in instruction execution cycle Register setting * ABRKCR2 = H'80 * BAR2 = H'025A Program 0258 * 025A 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP NOP : Underline indicates the address to be stacked. NOP MOV MOV NOP instruc- instruc- instruc- instruction tion 1 tion 2 Internal tion prefetch prefetch prefetch prefetch processing Address bus Interrupt request Interrupt acceptance Stack save 0258 025A 025C 025E SP-2 SP-4 Figure 21.2 Address Break Interrupt Operation Example (1) Rev. 1.00 Dec. 18, 2006 Page 447 of 568 REJ09B0348-0100 Section 21 Address Break When the address break is specified in the data read cycle Register setting * ABRKCR2 = H'A0 * BAR2 = H'025A Program 0258 025A * 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP Underline indicates the address NOP to be stacked. : MOV MOV NOP MOV NOP Next instruc- instruc- instruc- instruc- instruc- instrution 1 tion 2 tion tion tion ction Internal Stack prefetch prefetch prefetch execution prefetch prefetch processing save Address bus Interrupt request Interrupt acceptance 025C 025E 0260 025A 0262 0264 SP-2 Figure 21.2 Address Break Interrupt Operation Example (2) 21.3 Operating States of Address Break The operating states of the address break are shown in table 21.2. Table 21.2 Operating States of Address Break Operating Mode ABRKCR2 ABRKSR2 BAR2H BAR2L BDR2H BDR2L Reset Reset Reset Reset Reset Retained* Retained* Active Functions Functions Functions Functions Functions Functions Sleep Retained Retained Retained Retained Retained Retained Watch Retained Retained Retained Retained Retained Retained Subactive Functions Functions Functions Functions Functions Functions Sub-sleep Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby Retained Retained Retained Retained Retained Retained Note: * Undefined at a power-on reset Rev. 1.00 Dec. 18, 2006 Page 448 of 568 REJ09B0348-0100 Section 22 List of Registers Section 22 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. * * * * 2. * * * Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The data bus width is indicated. The number of access states is indicated. Register bits Bit configurations of the registers are described in the same order as the register addresses. Reserved bits are indicated by in the bit name column. When registers consist of 16 bits, bits are described from the MSB side. 3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. Rev. 1.00 Dec. 18, 2006 Page 449 of 568 REJ09B0348-0100 Section 22 List of Registers 22.1 Register Addresses (Address Order) The data bus width indicates the number of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Abbreviation SCR4 SCSR4 TDR4 RDR4 FLMCR1 FLMCR2 FLPWCR EBR1 FENR TSTR TSYR TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 8 8 8 8 8 16 Module Address Name H'F00C H'F00D H'F00E H'F00F H'F020 H'F021 H'F022 H'F023 H'F02B H'F030 H'F031 H'F040 H'F041 H'F042 H'F044 H'F045 H'F046 H'F048 H'F04A H'F050 H'F051 H'F052 H'F054 H'F055 H'F056 SCI4 SCI4 SCI4 SCI4 ROM ROM ROM ROM ROM TPU TPU TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 Data Bus Access Width State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 8 8 8 8 8 16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Serial control register 4 Serial control/status register 4 Transmit data register 4 Receive data register 4 Flash memory control register 1 Flash memory control register 2 Flash memory power control register Erase block register1 Flash memory enable register Timer start register Timer synchro register Timer control register_1 Timer mode register_1 Timer I/O control register_1 Timer interrupt enable register_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Rev. 1.00 Dec. 18, 2006 Page 450 of 568 REJ09B0348-0100 Section 22 List of Registers Register Name Timer general register A_2 Timer general register B_2 RTC interrupt flag register Second data register/free running counter data register Minute data register Hour data register Day-of-week data register RTC control register 1 RTC control register 2 SUB32k control register Clock source select register I2C bus control register 1 I C bus control register 2 I C bus mode register I C bus interrupt enable register I C bus status register Slave address register I C bus transmit data register I C bus receive data register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Address break control register 2 Address break status register 2 2 2 2 2 2 2 Abbreviation TGRA_2 TGRB_2 RTCFLG RSECDR RMINDR RHRDR RWKDR RTCCR1 RTCCR2 Bit No. 16 16 8 8 8 8 8 8 8 Module Address Name H'F058 H'F05A H'F067 H'F068 H'F069 H'F06A H'F06B H'F06C H'F06D H'F06E H'F06F H'F078 H'F079 H'F07A H'F07B H'F07C H'F07D H'F07E H'F07F H'F080 H'F081 H'F082 H'F083 H'F084 H'F096 H'F097 TPU_2 TPU_2 RTC RTC RTC RTC RTC RTC RTC Clock pulse generator RTC IIC2 IIC2 IIC2 IIC2 IIC2 IIC2 IIC2 IIC2 Interrupts Interrupts Interrupts Interrupts Interrupts Address break Address break Data Bus Access Width State 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SUB32CR 8 RTCCSR ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR IPRA IPRB IPRC IPRD IPRE 8 8 8 8 8 8 8 8 8 8 8 8 8 8 ABRKCR2 8 ABRKSR2 8 Rev. 1.00 Dec. 18, 2006 Page 451 of 568 REJ09B0348-0100 Section 22 List of Registers Register Name Break address register 2H Break address register 2L Break data register 2H Break data register 2L Event counter PWM compare register Event counter PWM data register Wakeup edge select register Serial port control register Input pin edge select register Event counter control register Event counter control/status register Event counter H Event counter L Serial mode register 3_1 Bit rate register 3_1 Serial control register 3_1 Transmit data register 3_1 Serial status register 3_1 Receive data register 3_1 IrDA control register Serial mode register 3_2 Bit rate register 3_2 Serial control register 3_2 Transmit data register 3_2 Serial status register 3_2 Receive data register 3_2 Timer mode register WD Abbreviation BAR2H BAR2L BDR2H BDR2L Bit No. 8 8 8 8 Module Address Name H'F098 H'F099 H'F09A H'F09B H'FF8C H'FF8E H'FF90 H'FF91 H'FF92 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF9A H'FF9B H'FF9C H'FF9D H'FFA7 H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFAD H'FFB0 Address break Address break Address break Address break AEC*1 AEC*1 Interrupts SCI3 AEC* AEC* AEC* AEC* AEC* 1 1 Data Bus Access Width State 8 8 8 8 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 2 ECPWCR 16 ECPWDR 16 WEGR SPCR AEGSR ECCR ECCSR ECH ECL SMR3_1 BRR3_1 SCR3_1 TDR3_1 SSR3_1 RDR3_1 IrCR SMR3_2 BRR3_2 SCR3_2 TDR3_2 SSR3_2 RDR3_2 TMWD 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1 1 1 SCI3_1 SCI3_1 SCI3_1 SCI3_1 SCI3_1 SCI3_1 IrDA SCI3_2 SCI3_2 SCI3_2 SCI3_2 SCI3_2 SCI3_2 WDT* 2 Rev. 1.00 Dec. 18, 2006 Page 452 of 568 REJ09B0348-0100 Section 22 List of Registers Register Name Timer control/status register WD1 Timer control/status register WD2 Timer counter WD Timer control register F Timer control/status register F 8-bit timer counter FH 8-bit timer counter FL Output compare register FH Output compare register FL A/D result register A/D mode register A/D start register Port mode register 1 Oscillator Control Register Port mode register 3 Port mode register 4 Port mode register 5 Port mode register 9 Port mode register B PWM2 control register PWM2 data register PWM1 control register PWM1 data register Port data register 1 Port data register 3 Port data register 4 Port data register 5 Port data register 6 Abbreviation Bit No. Module Address Name H'FFB1 H'FFB2 H'FFB3 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBE H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC8 H'FFCA H'FFCD H'FFCE H'FFD0 H'FFD2 H'FFD4 H'FFD6 H'FFD7 H'FFD8 H'FFD9 WDT*2 WDT* WDT* 2 2 Data Bus Access Width State 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 TCSRWD1 8 TCSRWD2 8 TCWD TCRF TCSRF TCFH TCFL OCRFH OCRFL ADRR AMR ADSR PMR1 OSCCR PMR3 PMR4 PMR5 PMR9 PMRB PWCR22 PWDR2 PWCR1 PWDR1 PDR1 PDR3 PDR4 PDR5 PDR6 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 16 8 16 8 8 8 8 8 Timer F Timer F Timer F Timer F Timer F Timer F A/D converter 16 A/D converter 8 A/D converter 8 I/O ports Clock pulse generator I/O ports I/O ports I/O ports I/O ports I/O ports 14-bit PWM 14-bit PWM 14-bit PWM 14-bit PWM I/O ports I/O ports I/O ports I/O ports I/O ports 8 8 8 8 8 8 8 8 16 8 16 8 8 8 8 8 Rev. 1.00 Dec. 18, 2006 Page 453 of 568 REJ09B0348-0100 Section 22 List of Registers Register Name Port data register 7 Port data register 8 Port data register 9 Port data register A Port data register B Port pull-up control register 1 Port pull-up control register 3 Port pull-up control register 5 Port pull-up control register 6 Port control register 1 Port control register 3 Port control register 4 Port control register 5 Port control register 6 Port control register 7 Port control register 8 Port control register 9 Port control register A System control register 1 System control register 2 IRQ edge select register Interrupt enable register 1 Interrupt enable register 2 Interrupt mask register Interrupt request register 1 Interrupt request register 2 Wakeup interrupt request register Clock stop register 1 Clock stop register 2 Abbreviation PDR7 PDR8 PDR9 PDRA PDRB PUCR1 PUCR3 PUCR5 PUCR6 PCR1 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PCR9 PCRA SYSCR1 SYSCR2 IEGR IENR1 IENR2 INTM IRR1 IRR2 IWPR Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Module Address Name H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFEC H'FFED H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFF9 H'FFFA H'FFFB I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports System System Interrupts Interrupts Interrupts Interrupts Interrupts Interrupts Interrupts System System Data Bus Access Width State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 CKSTPR1 8 CKSTPR2 8 Notes: 1. AEC: Asynchronous event counter 2. WDT: Watchdog timer Rev. 1.00 Dec. 18, 2006 Page 454 of 568 REJ09B0348-0100 Section 22 List of Registers 22.2 Register Bits Register bit names of the on-chip peripheral modules are described below. Register Abbreviation Bit 7 SCR4 SCSR4 TDR4 RDR4 FLMCR1 FLMCR2 FLPWCR EBR1 FENR TSTR TSYR TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1_ TCNT_1 TIE TDRE TDR47 RDR47 FLER Bit 6 RIE RDRF TDR46 RDR46 SWE Bit 5 TEIE ORER TDR45 RDR45 ESU EB5 CCLR0 IOB1 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 CCLR0 IOB1 Bit 4 SOL TEND TDR44 RDR44 PSU EB4 CKEG1 IOB0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 CKEG1 IOB0 TCIEV TCFV Bit 3 SOLP CKS3 TDR43 RDR43 EV EB3 CKEG0 IOA3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 CKEG0 IOA3 Bit 2 SRES CKS2 TDR42 RDR42 PV EB2 CST2 SYNC2 TPSC2 IOA2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 TPSC2 IOA2 Bit 1 TE CKS1 TDR41 RDR41 E EB1 CST1 SYNC1 TPSC1 MD1 IOA1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 0 RE CKS0 TDR40 RDR40 P EB0 TPSC0 MD0 IOA0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 TPSC0 MD0 IOA0 TGIEA TGFA TPU_2 TPU_1 TPU ROM Module Name SCI4 PDWND FLSHE IOB3 Bit15 Bit7 EB6 CCLR1 IOB2 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 CCLR1 IOB2 TGRA_1 Bit15 Bit7 TGRB_1 Bit15 Bit7 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 IOB3 Rev. 1.00 Dec. 18, 2006 Page 455 of 568 REJ09B0348-0100 Section 22 List of Registers Register Abbreviation Bit 7 TCNT_2 Bit15 Bit7 TGRA_2 Bit15 Bit7 TGRB_2 Bit15 Bit7 RTCFLG RSECDR RMINDR RHRDR RWKDR RTCCR1 RTCCR2 SUB32CR FOIFG BSY BSY BSY BSY RUN FOIE Module Name TPU_2 Bit 6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 WKIFG SC12 MN12 12/24 WKIE Bit 5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 DYIFG SC11 MN11 HR11 PM DYIE Bit 4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 HRIFG SC10 MN10 HR10 RST HRIE Bit 3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 MNIFG SC03 MN03 HR03 MNIE Bit 2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 SEIFG SC02 MN02 HR02 WK2 1SEIE Bit 1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit 0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 05SEIFG 025SEIFG RTC SC01 MN01 HR01 WK1 05SEIE SC00 MN00 HR00 WK0 025SEIE Clock pulse generator 32KSTOP RTCCSR ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR A IPRB IPRC IPRD IPRE ICE BBSY MLS TIE TDRE SVA6 ICDRT7 ICDRR7 IPRA7 IPRB7 IPRC7 IPRD7 IPRE7 RCS6 RCVD SCP WAIT TEIE TEND SVA5 ICDRT6 RCS5 MST SDAO RIE RDRF SVA4 ICDRT5 SUB32K RCS3 TRS SDAOP NAKIE NACKF SVA3 ICDRT4 ICDRR4 IPRA4 IPRB4 IPRC4 IPRD4 IPRE4 CKS3 SCLO BCWP STIE STOP SVA2 ICDRT3 ICDRR3 IPRA3 IPRB3 IPRC3 IPRD3 RCS2 CKS2 BC2 ACKE AL/OVE SVA1 ICDRT2 ICDRR2 IPRA2 IPRB2 IPRC2 IPRD2 RCS1 CKS1 IICRST BC1 ACKBR AAS SVA0 ICDRT1 ICDRR1 IPRA1 IPRB1 IPRC1 IPRD1 RCS0 CKS0 BC0 ACKBT ADZ FS ICDRT0 ICDRR0 IPRA0 IPRB0 IPRC0 IPRD0 RTC IIC2 ICDRR6 ICDRR5 IPRA6 IPRB6 IPRC6 IPRD6 IPRE6 IPRA5 IPRB5 IPRC5 IPRD5 IPRE5 Interrupts Rev. 1.00 Dec. 18, 2006 Page 456 of 568 REJ09B0348-0100 Section 22 List of Registers Register Abbreviation Bit 7 ABRKCR2 ABRKSR2 BAR2H BAR2L BDR2H BDR2L ECPWCR Module Name Bit 6 Bit 5 CSEL20 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RTINTE2 CSEL21 ABIF2 ABIE2 ACMP22 ACMP21 ACMP20 DCMP21 DCMP20 Address break BARH27 BARH26 BARH25 BARH24 BARH23 BARH22 BARH21 BARH20 BARL27 BARL26 BARL25 BARL24 BARL23 BARL22 BARL21 BARL20 BDRH27 BDRH26 BDRH25 BDRH24 BDRH23 BDRH22 BDRH21 BDRH20 BDRL27 BDRL26 BDRL25 BDRL24 BDRL23 BDRL22 BDRL21 BDRL20 ECPWCR15 ECPWCR14 ECPWCR13 ECPWCR12 ECPWCR11 ECPWCR10 ECPWCR9 ECPWCR8 AEC* 1 ECPWCR7 ECPWCR6 ECPWCR5 ECPWCR4 ECPWCR3 ECPWCR2 ECPWCR1 ECPWCR0 ECPWDR ECPWDR15 ECPWDR14 ECPWDR13 ECPWDR12 ECPWDR11 ECPWDR10 ECPWDR9 ECPWDR8 ECPWDR7 ECPWDR6 ECPWDR5 ECPWDR4 ECPWDR3 ECPWDR2 ECPWDR1 ECPWDR0 WEGR SPCR AEGSR ECCR ECCSR ECH ECL SMR3_1 BRR3_1 SCR3_1 TDR3_1 SSR3_1 RDR3_1 IrCR SMR3_2 BRR3_2 SCR3_2 TDR3_2 SSR3_2 RDR3_2 WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Interrupts SPC32 SPC31 SCINV3 SCINV2 AIEGS0 PWCK1 CUEL ECH2 ECL2 MP BRR2 TEIE TDR2 TEND RDR2 SCINV1 SCINV0 SCI3 AEC* 1 AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 ACKH1 OVH ECH7 ECL7 COM BRR7 TIE TDR7 TDRE RDR7 IrE COM32 ACKH0 OVL ECH6 ECL6 CHR BRR6 RIE TDR6 RDRF RDR6 IrCKS2 CHR32 ACKL1 ECH5 ECL5 PE BRR5 TE TDR5 OER RDR5 IrCKS1 PE32 ACKL0 CH2 ECH4 ECL4 PM BRR4 RE TDR4 FER RDR4 IrCKS0 PM32 PWCK2 CUEH ECH3 ECL3 STOP BRR3 MPIE TDR3 PER RDR3 ECPWME PWCK0 CRCH ECH1 ECL1 CKS1 BRR1 CKE1 TDR1 MPBR RDR1 CKS321 CRCL ECH0 ECL0 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 CKS320 IrDA SCI3_2 SCI3_1 STOP32 MP32 BRR327 BRR326 BRR325 BRR324 BRR323 BRR322 BRR321 BRR320 TIE32 TDR327 RIE32 TDR326 TE32 TDR325 RE32 TDR324 FER32 MPIE32 TDR323 PER32 TEIE32 TDR322 CKE321 TDR321 CKE320 TDR320 TDRE32 RDRF32 OER32 TEND32 MPBR32 MPBT32 RDR327 RDR326 RDR325 RDR324 RDR323 RDR322 RDR321 RDR320 Rev. 1.00 Dec. 18, 2006 Page 457 of 568 REJ09B0348-0100 Section 22 List of Registers Register Abbreviation Bit 7 TMWD TCSRWD1 TCSRWD2 TCWD TCRF TCSRF TCFH TCFL OCRFH OCRFL ADRR B6WI OVF TCW7 TOLH OVFH TCFH7 TCFL7 Module Name WDT* 2 Bit 6 TCWE B5WI TCW6 CKSH2 CMFH TCFH6 TCFL6 Bit 5 B4WI WT/IT TCW5 CKSH1 OVIEH TCFH5 TCFL5 Bit 4 Bit 3 CKS3 Bit 2 CKS2 WDON TCW2 CKSL2 CMFL TCFH2 TCFL2 Bit 1 CKS1 BOWI TCW1 CKSL1 OVIEL TCFH1 TCFL1 Bit 0 CKS0 WRST TCW0 CKSL0 CCLRL TCFH0 TCFL0 TCSRWE B2WI B3WI TCW4 CKSH0 CCLRH TCFH4 TCFL4 IEOVF TCW3 TOLL OVFL TCFH3 TCFL3 Timer F OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0 OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 ADR9 ADR1 ADR8 ADR0 TRGE ADR7 ADR6 ADR5 CH3 ADR4 CH2 ADR3 CH1 AEVL ADR2 CH0 AEVH -- I/O ports Clock pulse generator A/D converter AMR ADSR PMR1 OSCCR CKS ADSF IRQAECF OSCF PMR3 PMR4 PMR5 PMR9 PMRB PWCR22 PWDR2 WKP7 PWDR27 WKP6 PWDR26 PWDR16 WKP5 WKP4 ADTSTCHG WKP3 TMOFH WKP2 IRQ4 IRQ3 TMOFL WKP1 PWM2 IRQ1 TMOW TMIF WKP0 PWM1 IRQ0 I/O ports PWCR22 PWCR21 PWCR20 14-bit PWM PWDR213 PWDR212 PWDR211 PWDR210 PWDR29 PWDR28 PWDR25 PWDR24 PWDR23 PWDR22 PWCR12 PWDR21 PWCR11 PWDR20 PWCR10 PWDR18 PWDR10 PWCR1 PWDR1 PWDR17 PWDR113 PWDR112 PWDR111 PWDR110 PWDR19 PWDR15 PWDR14 PWDR13 PWDR12 PWDR11 Rev. 1.00 Dec. 18, 2006 Page 458 of 568 REJ09B0348-0100 Section 22 List of Registers Register Abbreviation Bit 7 PDR1 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB PUCR1 PUCR3 PUCR5 PUCR6 PCR1 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PCR9 PCRA SYSCR1 SYSCR2 IEGR IENR1 IENR2 INTM IRR1 P37 P57 P67 P77 P87 PB7 Module Name I/O ports Bit 6 P16 P36 P56 P66 P76 P86 PB6 Bit 5 P15 P55 P65 P75 P85 PB5 Bit 4 P14 P54 P64 P74 P84 PB4 Bit 3 P13 P53 P63 P73 P83 P93 PA3 PB3 Bit 2 P12 P32 P42 P52 P62 P72 P82 P92 PA2 PB2 Bit 1 P11 P31 P41 P51 P61 P71 P81 P91 PA1 PB1 Bit 0 P10 P30 P40 P50 P60 P70 P80 P90 PA0 PB0 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 PUCR30 PUCR37 PUCR36 PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 PCR37 PCR57 PCR67 PCR77 PCR87 SSBY NMIEG IENRTC IENDT PCR16 PCR36 PCR56 PCR66 PCR76 PCR86 STS2 TMIFG IENAD PCR15 PCR55 PCR65 PCR75 PCR85 STS1 ADTRGNEG PCR14 PCR54 PCR64 PCR74 PCR84 STS0 NESEL IEG4 IEN4 IRR4 PCR13 PCR53 PCR63 PCR73 PCR83 PCR93 PCRA3 LSON DTON IEG3 IEN3 IENTFH IRR3 PCR12 PCR32 PCR42 PCR52 PCR62 PCR72 PCR82 PCR92 PCRA2 TMA3 MSON IENEC2 IENTFL IRREC2 PCR11 PCR31 PCR41 PCR51 PCR61 PCR71 PCR81 PCR91 PCRA1 MA1 SA1 IEG1 IEN1 INTM1 IRRI1 PCR10 PCR30 PCR40 PCR50 PCR60 PCR70 PCR80 PCR90 PCRA0 MA0 SA0 IEG0 IEN0 IENEC INTM0 IRRI0 Interrupts System IENWP -- Rev. 1.00 Dec. 18, 2006 Page 459 of 568 REJ09B0348-0100 Section 22 List of Registers Register Abbreviation Bit 7 IRR2 IWPR CKSTPR1 CKSTPR2 IRRDT IWPF7 S4CKSTP* 3 Bit 6 IRRAD IWPF6 S31CKSTP TPUCKSTP Bit 5 -- IWPF5 S32CKSTP IICCKSTP Bit 4 IWPF4 ADCKSTP Bit 3 Bit 2 Bit 1 Bit 0 IRREC IWPF0 3 Module Name Interrupts IRRTFH IRRTFL IWPF3 -- IWPF2 TFCKSTP WDCKSTP IWPF1 FROMCKSTP* PW1CKSTP RTCCKSTP LDCKSTP System ADBCKSTP PW2CKSTP AECCKSTP Notes: 1. AEC: Asynchronous event counter 2. WDT: Watchdog timer 3. This bit is available only for the flash memory version. In the masked ROM version, this bit is reserved. Rev. 1.00 Dec. 18, 2006 Page 460 of 568 REJ09B0348-0100 Section 22 List of Registers 22.3 Register States in Each Operating Mode Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Active Sleep Watch Subactive Subsleep Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized TPU_2 TPU_1 TPU ROM Module SCR4 Register Abbreviation SCR4 SCSR4 TDR4 RDR4 FLMCR1 FLMCR2 FLPWCR EBR1 FENR TSTR TSYR TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1_ TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 Rev. 1.00 Dec. 18, 2006 Page 461 of 568 REJ09B0348-0100 Section 22 List of Registers Register Abbreviation RTCFLG RSECDR RMINDR RHRDR RWKDR RTCCR1 RTCCR2 SUB32CR RTCCSR ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR IPRA IPRB IPRC IPRD IPRE ABRKCR2 ABRKSR2 BAR2H BAR2L BDR2H BDR2L ECPWCR ECPWDR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Active Sleep Watch Subactive Subsleep Standby Module RTC Clock pulse generator RTC IIC2 Interrupts Address break AEC* 1 Rev. 1.00 Dec. 18, 2006 Page 462 of 568 REJ09B0348-0100 Section 22 List of Registers Register Abbreviation WEGR SPCR AEGSR ECCR ECCSR ECH ECL SMR3_1 BRR3_1 SCR3_1 TDR3_1 SSR3_1 RDR3_1 IrCR SMR3_2 BRR3_2 SCR3_2 TDR3_2 SSR3_2 RDR3_2 TMWD TCSRWD1 TCSRWD2 TCWD TCRF TCSRF TCFH TCFL OCRFH OCRFL Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Active Sleep Watch Subactive Subsleep Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Interrupts SCI3 AEC* 1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI3_1 IrDA SCI3_2 WDT* 2 Timer F Rev. 1.00 Dec. 18, 2006 Page 463 of 568 REJ09B0348-0100 Section 22 List of Registers Register Abbreviation ADRR AMR ADSR PMR1 PMR3 PMR4 PMR5 PMR9 PMRB PWCR2 PWDR2 PWCR1 PWDR1 PDR1 OSCCR PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB PUCR1 PUCR3 PUCR5 PUCR6 PCR1 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Active Sleep Watch Subactive Subsleep Standby Module A/D converter I/O ports 14-bit PWM I/O ports Clock pulse generator I/O ports Rev. 1.00 Dec. 18, 2006 Page 464 of 568 REJ09B0348-0100 Section 22 List of Registers Register Abbreviation PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PCR9 PCRA SYSCR1 SYSCR2 IEGR IENR1 IENR2 INTM IRR1 IRR2 IWPR CKSTPR1 CKSTPR2 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Active Sleep Watch Subactive Subsleep Standby Module I/O ports System Interrupts System Notes: is not initialized. 1. AEC: Asynchronous event counter 2. WDT: Watchdog timer Rev. 1.00 Dec. 18, 2006 Page 465 of 568 REJ09B0348-0100 Section 22 List of Registers Rev. 1.00 Dec. 18, 2006 Page 466 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Section 23 Electrical Characteristics 23.1 Absolute Maximum Ratings for F-ZTAT Version Table 23.1 lists the absolute maximum ratings. Table 23.1 Absolute Maximum Ratings Item Power supply voltage Analog power supply voltage Input voltage Other than port B Port B Operating temperature Symbol VCC AVCC Vin AVin Topr Value -0.3 to +4.3 -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -20 to +75 (regular specifications)*2 -40 to +85 (wide-range specifications)*2 Storage temperature Tstg -55 to +125 C Unit Note V V V V C *1 Notes: 1. Permanent damage may occur to the chip if absolute maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 2. When the operating voltage (Vcc) for reading the flash memory is from 2.7 V to 3.6 V, the operating temperature (Ta) for programming/erasing ranges from -20 to +75C. When the operating voltage (Vcc) for reading the flash memory is from 1.8 V to 3.6 V, the operating temperature (Ta) for programming/erasing ranges from -20 to +50C. Rev. 1.00 Dec. 18, 2006 Page 467 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics 23.2 23.2.1 Electrical Characteristics for F-ZTAT Version Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. (1) Power Supply Voltage and Oscillation Frequency Range [10-MHz version] 38.4 fosc (MHz) fW (kHz) 1.8 2.7 3.6 VCC (V) 32.768 10.0 4.2 2.0 1.8 * All operating mode 2.7 3.6 VCC (V) * Active (high-speed) mode * Sleep (high-speed) mode * Refer to no.1 in the note. [4-MHz version] * Refer to no. 2 in the note. Notes: 1.The fosc values are those when a resonator is used; when an external clock is used, the minimum value of fosc is 1 MHz. 2. When a resonator is used, hold VCC at 2.2 V to 3.6 V from power-on until the oscillation settling time has elapsed. fosc (MHz) 10.0 4.2 2.0 1.8 2.7 3.6 VCC (V) * Active (high-speed) mode * Sleep (high-speed) mode * Refer to no.1 in the note. Rev. 1.00 Dec. 18, 2006 Page 468 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics (2) Power Supply Voltage and Operating Frequency Range [10-MHz version] (MHz) 10 4.2 19.2 16.384 2.0 (1.0) SUB (kHz) 1.8 2.7 3.6 VCC (V) 9.6 * Active (high-speed) mode * Sleep (high-speed) mode (except CPU) * Refer to no.1 in the note. 8.192 4.8 (MHz) 1250 525 4.096 1.8 31.25 (15.625) 1.8 2.7 3.6 VCC (V) 2.7 3.6 VCC (V) * Active (medium-speed) mode * Sleep (medium-speed) mode (except A/D converter) * Refer to no.2 in the note. * Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU) [4-MHz version] Notes: 1. The value in parentheses is the minimum operating frequency when an external clock is input. When using a resonator, the minimum operating frequency ( ) is 1 MHz 2. The value in parentheses is the minimum operating frequency when an external clock is input. When using a resonator, the minimum operating frequency ( ) is 31.25 kHz. (MHz) 10 4.2 2.0 (1.0) 1.8 2.7 3.6 VCC (V) * Active (high-speed) mode * Sleep (high-speed) mode (except CPU) * Refer to no.1 in the note. (MHz) 1250 525 31.25 (15.625) 1.8 2.7 3.6 VCC (V) * Active (medium-speed) mode * Sleep (medium-speed) mode (except A/D converter) * Refer to no.2 in the note. Rev. 1.00 Dec. 18, 2006 Page 469 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics (3) Analog Power Supply Voltage and A/D Converter Operating Frequency Range [10-MHz version] 10.0 (MHz) (MHz) 1250 31.25 (15.625) 2.7 3.6 AVCC(V) 4.2 2.0 (1.0) 1.8 2.7 3.6 AVCC(V) * Active (high-speed) mode * Sleep (high-speed) mode * Refer to no.1 in the note. [4-MHz version] * Active (medium-speed) mode * Sleep (medium-speed) mode * Refer to no.2 in the note. 10.0 (MHz) 4.2 (MHz) 2.0 (1.0) 1.8 2.7 3.6 AVCC(V) 525 31.25 (15.625) 2.7 3.6 AVCC(V) * Active (high-speed) mode * Sleep (high-speed) mode * Refer to no.1 in the note. * Active (medium-speed) mode * Sleep (medium-speed) mode * Refer to no.2 in the note. Notes: 1. The minimum operating frequency () is 2 MHz when using a resonator; and 1 MHz when using an external clock. 2. The minimum operating frequency () is 31.25 kHz when using a resonator; and 15.625 kHz when using an external clock. Rev. 1.00 Dec. 18, 2006 Page 470 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics 23.2.2 DC Characteristics Table 23.2 lists the DC characteristics. Table 23.2 DC Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Values Item Input high voltage Symbol VIH Applicable Pins RES, NMI* , WKP0 3 Test Condition Min. 0.9VCC Typ. -- Max. VCC + 0.3 Unit V Notes to WKP7, IRQ0, AEVL, AEVH, TMIF, ADTRG, SCK32, SCK31, SCK4 IRQ1, IRQ3, IRQ4 RXD32, RXD31 OSC1 X1 P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P93, PA0 to PA3, TCLKA, TCLKB, TCLKC, TIOCA1, TIOCA2, TIOCB1, TIOCB2, SCL, SDA PB0 to PB7 IRQAEC 0.8VCC 0.9VCC -- -- AVCC + 0.3 VCC + 0.3 VCC = 2.7 to 3.6 V 0.9VCC 0.8VCC 0.9VCC 0.9VCC 0.8VCC -- -- -- -- -- AVCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 Rev. 1.00 Dec. 18, 2006 Page 471 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Applicable Item Input low voltage Symbol VIL Pins RES, NMI* , 3 Values Test Condition Min. -0.3 Typ. -- Max. 0.1VCC Unit V Notes WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, AEVL, AEVH, TMIF, ADTRG, SCK32, SCK31, SCK4 RXD32, RXD31 OSC1 X1 P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P93, PA0 to PA3, TCLKA, TCLKB, TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2, SCL, SDA, PB0 to PB7 VCC = 2.7 to 3.6 V -0.3 -0.3 -0.3 -0.3 -- -- -- -- 0.2VCC 0.1VCC 0.1VCC 0.2VCC Output high voltage VOH P10, P16, P30 to P32, P36, P37 P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 P90 to P93 -IOH = 1.0 mA VCC = 2.7 to 3.6 V -IOH = 0.1 mA VCC - 1.0 -- -- V VCC - 0.3 -- -- IOH = 1.0 mA VCC = 2.7 to 3.6 V IOH = 0.1 mA VCC - 1.0 -- -- VCC - 0.3 -- -- Rev. 1.00 Dec. 18, 2006 Page 472 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Applicable Item Output low voltage Symbol VOL Pins P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 P90 to P93 IOL = 15 mA, VCC = 2.7 to 3.6 V IOL = 10 mA, VCC = 2.2 to 3.6 V IOL = 8 mA VCC = 1.8 to 3.6 V SCL, SDA VCC = 2.0 to 3.6 V IOL = 3.0 mA VCC = 1.8 to 2.0 V IOL = 3.0 mA Input/output leakage current | IIL | NMI*3, OSC1, X1, P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, IRQAEC, PA0 to PA3, P90 to P93 PB0 to PB7 VIN = 0.5 V to AVCC - 0.5 V Pull-up MOS -Ip current P10 to P16, P30, P36, P37, P50 to P57, P60 to P67 VCC = 3.0 V, VIN = 0 V 30 -- VIN = 0.5 V to VCC - 0.5 V -- -- -- -- -- -- Test Condition IOL = 0.4 mA Min. -- Values Typ. -- Max. 0.5 Unit V Notes -- 1.0 -- 0.5 -- 0.5 -- 0.4 -- 0.2VCC -- 1.0 A -- 1.0 -- 180 A Rev. 1.00 Dec. 18, 2006 Page 473 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Applicable Item Input capacitance*4 Symbol CIN Pins All input pins except power supply pin Active mode supply current IOPE1 VCC Test Condition f = 1 MHz, VIN =0 V, Ta = 25C Active (high-speed) mode, VCC = 1.8 V, fOSC = 2 MHz Active (high-speed) mode, VCC = 3.0 V, fOSC = 4 MHz Active (high-speed) mode, VCC = 3.0 V, fOSC = 10 MHz IOPE2 VCC Active (mediumspeed) mode, VCC = 1.8 V, fOSC = 2 MHz, osc/64 Active (mediumspeed) mode, VCC = 3.0 V, fOSC = 4 MHz, osc/64 Active (mediumspeed) mode, VCC = 3.0 V, fOSC = 10 MHz, osc/64 Sleep mode supply current ISLEEP VCC VCC= 1.8 V, fOSC= 2 MHz -- -- -- -- -- -- -- Min. -- Values Typ. -- Max. 15.0 Unit pF Notes 1.1 -- mA *1*2*5 Max. guideline = 1.1 x typ. 3.0 -- *1*2 Max. guideline = 1.1 x typ. 6.6 10 *1*2 0.4 -- mA *1*2*5 Max. guideline = 1.1 x typ. 0.7 -- *1*2 Max. guideline = 1.1 x typ. 1.1 1.8 *1*2 0.7 -- mA *1*2*5 Max. guideline = 1.1 x typ. VCC= 3.0 V, fOSC= 4 MHz -- 1.7 -- *1*2 Max. guideline = 1.1 x typ. VCC= 3.0 V, fOSC= 10 MHz -- 3.5 5.0 *1*2 Rev. 1.00 Dec. 18, 2006 Page 474 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Applicable Item Subactive mode supply current Symbol ISUB Pins VCC Test Condition VCC = 1.8 V, 32-kHz crystal resonator is used (SUB = w/2) VCC = 2.7 V, 32-kHz crystal resonator is used (SUB = w/8) VCC = 2.7 V, 32-kHz crystal resonator is used (SUB = w/2) Subsleep mode supply current ISUBSP VCC VCC = 2.7 V, 32-kHz crystal resonator is used (SUB = w/2) Watch mode supply current IWATCH VCC VCC = 1.8 V, Ta = 25C, 32-kHz crystal resonator not used VCC = 2.7 V, 32-kHz crystal resonator not used Standby mode ISTBY supply current VCC VCC = 1.8 V, Ta = 25C, 32-kHz crystal resonator not used VCC = 3.0 V, Ta = 25C, 32-kHz crystal resonator not used 32-kHz crystal resonator not used VCC = 3.0 V, 32KSTOP = 1 -- -- -- -- -- -- -- -- -- Min. -- Values Typ. 19 Max. -- Unit A Notes *1*2 Reference value 6.8 -- *1*2 Reference value 23 50 *1*2 4.3 16.0 A *1*2 0.4 -- A *1*2*5 Reference value 1.5 6.0 *1*2 0.4 -- A *1*2 Reference value 0.6 -- *1*2 Reference value 1.0 5.0 *1*2 0.3 -- *1*2 Reference value Rev. 1.00 Dec. 18, 2006 Page 475 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Applicable Item RAM data retaining voltage Allowable output low current (per pin) Allowable output low current (total) Allowable output high current (per pin) Allowable output high current (total) - IOH All output pins -- VCC = 1.8 V to 3.6 V -- -IOH IOL IOL Output pins except port 9 P90 to P93 Output pins except port 9 Port 9 All output pins VCC = 2.7 V to 3.6 V -- -- -- -- -- Symbol VRAM Pins VCC Test Condition Min. 1.5 Values Typ. -- Max. -- Unit V Notes -- 0.5 mA -- -- 15.0 20.0 mA -- -- -- 60.0 2.0 0.2 mA -- 10.0 mA Rev. 1.00 Dec. 18, 2006 Page 476 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Notes: 1. Pin states during current measurement. Mode Active (high-speed) mode (IOPE1) Active (medium-speed) mode (IOPE2) Sleep mode VCC Only on-chip timers operate On-chip WDT oscillator is off Subactive mode VCC Only CPU operates On-chip WDT oscillator is off Subsleep mode VCC Only on-chip timers operate, CPU stops On-chip WDT oscillator is off Watch mode VCC Only time base operates, CPU stops On-chip WDT oscillator is off Standby mode VCC CPU and timers both stop On-chip WDT oscillator is off VCC System clock oscillator: crystal resonator Subclock oscillator: Pin X1 = GND (32KSTOP = 0) VCC VCC VCC System clock oscillator: crystal resonator Subclock oscillator: crystal resonator VCC RES Pin VCC Internal State Only CPU operates On-chip WDT oscillator is off Other Pins VCC Oscillator Pins System clock oscillator: crystal resonator Subclock oscillator: Pin X1 = GND 2. 3. 4. 5. Excludes current in pull-up MOS transistors and output buffers. Used for the determination of user mode or boot mode when the reset is released. Except for the package for the TLP-85V. Only for 4-MHz version. Rev. 1.00 Dec. 18, 2006 Page 477 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics 23.2.3 AC Characteristics Table 23.3 lists the control signal timing, table 23.4 lists the serial interface timing, and table 23.5 lists the I2C bus interface timing. Table 23.3 Control Signal Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Applicable Item System clock oscillation frequency VCC = 1.8 to 3.6 V OSC clock (OSC) cycle tOSC time VCC = 1.8 to 3.6 V 238 -- OSC1, OSC2 VCC = 2.7 to 3.6 V 2.0 100 -- -- 4.2 500 (1000) 500 (1000) System clock () cycle tcyc time Subclock oscillation frequency Watch clock (W) cycle tW time Subclock (SUB) cycle time Instruction cycle time 2 -- -- tcyc tsubcyc Oscillation stabilization trc time OSC1, OSC2 Crystal resonator (VCC = 2.7 to 3.6 V) Crystal resonator (VCC = 2.2 to 3.6 V) Ceramic resonator (VCC = 2.2 to 3.6 V) Ceramic resonator (other than above) Other than above x1, x2 VCC = 2.2 to 3.6 V Other than above -- -- -- -- -- 4 50 2.0 -- ms s Figure 5.7 -- 80 -- -- 20 45 s Figure 23.10 -- 1.2 3 -- 0.8 2.0 ms Figure 23.10 tsubcyc 2 X1, X2 -- fW X1, X2 1 -- -- -- -- 64 64 tOSC s kHz ns Figure 23.2 *2 Symbol fOSC Pins OSC1, OSC2 Test Condition VCC = 2.7 to 3.6 V Min. 2.0 Values Typ. -- Max. 10.0 Unit MHz Reference Figure 32.768 -- or 38.4 30.5 or -- 26.0 -- 8 s Figure 23.2 tW *1 Rev. 1.00 Dec. 18, 2006 Page 478 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Applicable Item External clock high width VCC = 1.8 to 3.6 V X1 95 -- Symbol tCPH Pins OSC1 Test Condition VCC = 2.7 to 3.6 V Min. 40 Values Typ. -- Max. -- Reference Item Figure ns Figure 23.2 -- 15.26 or 13.02 -- -- s External clock low width tCPL OSC1 VCC = 2.7 to 3.6 V 40 -- -- ns Figure 23.2 VCC = 1.8 to 3.6 V X1 95 -- -- 15.26 or 13.02 -- -- s External clock F time tCPr OSC1 VCC = 2.7 to 3.6 V VCC = 1.8 to 3.6 V -- -- -- -- -- -- -- -- -- -- 10 24 55.0 10 24 55.0 -- ns Figure 23.2 X1 External clock fall time tCPf OSC1 VCC = 2.7 to 3.6 V VCC = 1.8 to 3.6 V X1 RES pin low width tREL RES IRQ0, IRQ1, NMI, IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, TMIF, ADTRG AEVL, AEVH VCC = 2.7 to 3.6 V VCC = 1.8 to 3.6 V tTCKWH TCLKA, TCLKB, Single edge TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2 Both edges specified specified -- -- -- 10 ns Figure 23.2 tcyc Figure 23.3*3 Input pin high width tIH 2 -- -- tcyc tsubcyc Figure 23.4 50 110 1.5 -- -- -- -- -- -- ns tcyc Figure 23.7 2.5 -- -- Rev. 1.00 Dec. 18, 2006 Page 479 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Applicable Item Input pin low width Symbol tIL Pins IRQ0, IRQ1, NMI, IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, TMIF, ADTRG AEVL, AEVH VCC = 2.7 to 3.6 V VCC = 1.8 to 3.6 V tTCKWL TCLKA, TCLKB, Single edge TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2 Both edges specified 2.5 specified 50 110 1.5 Test Condition Min. 2 Values Typ. -- Max. -- Item tcyc tsubcyc Reference Figure Figure 23.4 -- -- -- -- -- -- ns tcyc Figure 23.7 -- -- Notes: 1. Selected with the SA1 and SA0 bits in the system control register 2 (SYSCR2). 2. The value in parentheses is tOSC (max.) when an external clock is used. 3. For details on the power-on reset characteristics, refer to table 23.7 and figure 23.1. Table 23.4 Serial Interface Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Values Item Input clock cycle Asynchronous Clocked synchronous Input clock pulse width Transmit data delay time (clocked synchronous) Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous) tRXH VCC = 2.7 to 3.6 V tRXS VCC = 2.7 to 3.6 V 238 100 238 100 -- -- ns Figure 23.6 -- -- tSCKW tTXD 0.4 -- 0.4 -- -- -- 0.6 1 tscyc tcyc or tsubcyc ns Figure 23.6 Figure 23.5 Figure 23.6 Symbol tscyc Test Condition Min. 4 6 Typ. -- -- Max. -- -- Unit tcyc or tsubcyc Reference Figure Figure 23.5 Rev. 1.00 Dec. 18, 2006 Page 480 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Table 23.5 I2C Bus Interface Timing VCC = 1.8 V to 3.6 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise specified. Test Item SCL input cycle time SCL input high width SCL input low width Symbol tSCL tSCLH tSCLL Condition Min. 12tcyc + 600 3tcyc + 300 5tcyc + 300 -- -- Values Typ. -- -- -- -- -- Max. -- -- -- 300 1tcyc -- Unit ns ns ns ns ns Reference Figure Figure 23.8 SCL and SDA input fall time tSf SCL and SDA input spike pulse removal time SDA input bus-free time Start condition input hold time Retransmission start condition input setup time tSP tBUF tSTAH tSTAS 5tcyc 3tcyc 3tcyc 3tcyc 1tcyc + 20 0 0 -- ns -- -- ns -- -- ns Setup time for stop condition tSTOS input Data-input setup time Data-input hold time Capacitive load of SCL and SDA SCL and SDA output fall time tSDAS tSDAH Cb -- -- ns -- -- -- -- -- 400 ns ns pF tSf -- -- 300 ns 23.2.4 A/D Converter Characteristics Table 23.6 lists the A/D converter characteristics. Rev. 1.00 Dec. 18, 2006 Page 481 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Table 23.6 A/D Converter Characteristics VCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Applicable Item Analog power supply voltage Analog input voltage Analog power supply current Symbol AVCC AVIN AIOPE AISTOP1 Pins AVCC AN0 to AN7 AVCC AVCC AVCC = 3.0 V Test Condition Min. 1.8 -0.3 -- -- Values Typ. -- -- -- 600 Max. 3.6 AVCC + 0.3 1.0 -- Unit V V mA A * 2 Notes * 1 Reference value AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) Nonlinearity error AVCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V AVCC = 2.0 V to 3.6 V VCC = 2.0 V to 3.6 V Other than above Quantization error Absolute accuracy AVCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V AVCC = 2.0 V to 3.6 V VCC = 2.0 V to 3.6 V Other than above Conversion time AVCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V AVCC = 2.0 V to 3.6 V VCC = 2.0 V to 3.6 V Other than above CAIN RAIN AVCC AN0 to AN7 -- -- -- -- -- -- 5 15.0 10.0 A pF k * 3 -- -- -- -- -- -- -- -- 6.2 14.7 31 -- -- -- -- -- -- -- -- -- -- -- 10 3.5 5.5 7.5 0.5 4.0 6.0 8.0 124 124 124 bits LSB * LSB LSB 4 * s 4 Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at a reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle. 4. Conversion time = 62 s Rev. 1.00 Dec. 18, 2006 Page 482 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics 23.2.5 Power-On Reset Circuit Characteristics Table 23.7 lists the power-on reset circuit characteristics. Table 23.7 Power-On Reset Circuit Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications), unless otherwise specified. Values Item Reset voltage Symbol V_rst Test Condition Min. 0.7Vcc Typ. 0.8Vcc Max. 0.9Vcc Unit V Notes Power supply rise time t_vtr The Vcc rise time should be shorter than half the RES rise time. Reset count time Count start time t_out t_cr 0.8 -- 4.0 s Adjustable by the value of the external capacitor of the RES pin. On-chip pull-up resistance Rp Vcc = 3.0 V 60 100 -- k 23.2.6 Watchdog Timer Characteristics Table 23.8 Watchdog Timer Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications), unless otherwise specified. Applicable Item On-chip oscillator overflow time Symbol tovf Pins Test Condition Min. 0.2 Values Typ. 0.4 Max. -- Unit s Notes Rev. 1.00 Dec. 18, 2006 Page 483 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics 23.2.7 Flash Memory Characteristics Table 23.9 lists the flash memory characteristics. Table 23.9 Flash Memory Characteristics Condition A: AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 3.6 V (operating voltage range in reading), VCC = 3.0 V to 3.6 V (operating voltage range in programming/erasing), Ta = -20 to +75C (operating temperature range in programming/erasing: regular specifications, wide-range specifications) Condition B: AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, VCC = 1.8 V to 3.6 V (operating voltage range in reading), VCC = 3.0 V to 3.6 V (operating voltage range in programming/erasing), Ta = -20 to +50C (operating temperature range in programming/erasing: regular specifications, wide-range specifications) Item Programming time (per 128 bytes)*1*2*4 Erase time (per block)*1*3*6 Maximum number of reprogrammings Symbol tP tE NWEC tDRP x y z1 z2 z3 Wait time after P bit clear*1 Wait time after PSU bit clear*1 Wait time after PV bit setting*1 Wait time after dummy write*1 Wait time after PV bit clear*1 Wait time after SWE bit clear*1 Maximum programming count*1*4*5 N 1n6 7 n 1000 Additionalprogramming Test Condition Values Min. -- -- 1000*8*11 100* * Data retention time Programming Wait time after SWE bit setting*1 Wait time after PSU bit setting*1 Wait time after P bit setting*1*4 10*10 1 50 28 198 8 5 5 4 2 2 100 -- 8 12 Typ. 7 100 Max. 200 1200 Unit ms ms Times 10000*9 -- 10000* -- -- -- -- 30 200 10 -- -- -- -- -- -- -- -- -- -- 32 202 12 -- -- -- -- -- -- 1000 9 Years s s s s s s s s s s s Times Rev. 1.00 Dec. 18, 2006 Page 484 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Values Min. 1 100 10 10 10 20 2 4 100 -- Typ. -- -- -- -- -- -- -- -- -- -- Max. -- -- 100 -- -- -- -- -- -- 120 Unit s s ms s s s s s s Times Item Erase Wait time after SWE bit setting* 1 Symbol x y z N Test Condition Wait time after ESU bit setting*1 Wait time after E bit setting*1*6 Wait time after E bit clear* 1 Wait time after ESU bit clear*1 Wait time after EV bit setting* 1 Wait time after dummy write*1 Wait time after EV bit clear*1 Wait time after SWE bit clear*1 Maximum erase count*1*6*7 Notes: 1. 2. Make the time settings in accordance with the program/erase algorithms. The programming time for 128 bytes. (Indicates the total time for which the P bit in the flash memory control register 1 (FLMCR1) is set. The program-verify time is not included.) 3. The time required to erase one block. (Indicates the total time for which the E bit in the flash memory control register 1 (FLMCR1) is set. The erase-verify time is not included.) 4. Programming time maximum value (tP (max.)) = wait time after P bit setting (z) x maximum number of programmings (N) 5. Set the maximum number of programmings (N) according to the actual set values of z1, z2, and z3, so that it does not exceed the programming time maximum value (tP (max.)). The wait time after P bit setting (z1, z2) should be changed as follows according to the value of the number of programmings (n). Number of programmings (n) 1n6 z1 = 30 s 7 n 1000 z2 = 200 s 6. Erase time maximum value (tE (max.)) = wait time after E bit setting (z) x maximum number of erases (N) 7. Set the maximum number of erases (N) according to the actual set value of (z), so that it does not exceed the erase time maximum value (tE (max.)). 8. The minimum number of times in which all characteristics are guaranteed following reprogramming. (The guarantee covers the range from 1 to the minimum value.) 9. Reference value at 25C. (Guideline showing number of reprogrammings over which functioning will be retained under normal circumstances.) 10. Data retention characteristics within the range indicated in the specifications, including the minimum value for reprogrammings. 11. Applies to an operating voltage range when reading data of 2.7 to 3.6 V. 12. Applies to an operating voltage range when reading data of 1.8 to 3.6 V. Rev. 1.00 Dec. 18, 2006 Page 485 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics 23.3 Absolute Maximum Ratings for Masked ROM Version Table 23.10 lists the absolute maximum ratings. Table 23.10 Absolute Maximum Ratings Item Power supply voltage Analog power supply voltage Input voltage Other than port B Port B Operating temperature Symbol VCC AVCC Vin AVin Topr Value -0.3 to +4.3 -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -20 to +75 (regular specifications) -40 to +85 (wide-range specifications) Storage temperature Tstg -55 to +125 C Unit V V V V C Note *1 Note: Permanent damage may occur to the chip if absolute maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. Rev. 1.00 Dec. 18, 2006 Page 486 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics 23.4 23.4.1 Electrical Characteristics for Masked ROM Version Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. (1) Power Supply Voltage and Oscillation Frequency Range 38.4 fosc (MHz) fW (kHz) 1.8 2.7 3.6 VCC (V) 32.768 10.0 4.2 2.0 1.8 2.7 3.6 VCC (V) * Active (high-speed) mode * Sleep (high-speed) mode * Refer to no.1 in the note. * All operating mode * Refer to no.2 in the note. Notes: 1.The fosc values are those when a resonator is used; when an external clock is used, the minimum value of fosc is 1 MHz. 2. When a resonator is used, hold VCC at 2.2 V to 3.6 V from power-on until the oscillation settling time has elapsed. Rev. 1.00 Dec. 18, 2006 Page 487 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics (2) Power Supply Voltage and Operating Frequency Range (MHz) 10 4.2 19.2 16.384 2.0 (1.0) SUB (kHz) 1.8 2.7 3.6 VCC (V) 9.6 * Active (high-speed) mode * Sleep (high-speed) mode (except CPU) * Refer to no.1 in the note. (MHz) 8.192 4.8 1250 525 4.096 1.8 31.25 (15.625) 1.8 2.7 3.6 VCC (V) 2.7 3.6 VCC (V) * Active (medium-speed) mode * Sleep (medium-speed) mode (except A/D converter) * Refer to no.2 in the note. * Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU) Notes: 1. The value in parentheses is the minimum operating frequency when an external clock is input. When using a resonator, the minimum operating frequency ( ) is 1 MHz 2. The value in parentheses is the minimum operating frequency when an external clock is input. When using a resonator, the minimum operating frequency ( ) is 31.25 kHz. Rev. 1.00 Dec. 18, 2006 Page 488 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics (3) Analog Power Supply Voltage and A/D Converter Operating Frequency Range 10.0 1250 (MHz) 4.2 (MHz) 1.8 2.7 3.6 AVCC(V) 525 2.0 (1.0) 31.25 (15.625) 2.7 3.6 AVCC(V) * Active (high-speed) mode * Sleep (high-speed) mode * Refer to no.1 in the note. * Active (medium-speed) mode * Sleep (medium-speed) mode * Refer to no.2 in the note. Notes: 1. The minimum operating frequency () is 2 MHz when using a resonator; and 1 MHz when using an external clock. 2. The minimum operating frequency () is 31.25 kHz when using a resonator; and 15.625 kHz when using an external clock. Rev. 1.00 Dec. 18, 2006 Page 489 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics 23.4.2 DC Characteristics Table 23.11 lists the DC characteristics. Table 23.11 DC Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Values Item Input high voltage Symbol VIH Applicable Pins RES, NMI, WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, AEVL, AEVH, TMIF, ADTRG, SCK32, SCK31 RXD32, RXD31 OSC1 X1 P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P93, PA0 to PA3, TCLKA, TCLKB, TCLKC, TIOCA1, TIOCA2, TIOCB1, TIOCB2, SCL, SDA PB0 to PB7 IRQAEC 0.8VCC 0.9VCC -- -- AVCC + 0.3 VCC + 0.3 VCC = 2.7 to 3.6 V 0.8VCC 0.9VCC 0.9VCC 0.8VCC -- -- -- -- VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 Test Condition Min. 0.9VCC Typ. -- Max. VCC + 0.3 Unit V Notes Rev. 1.00 Dec. 18, 2006 Page 490 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Values Item Input low voltage Symbol VIL Applicable Pins RES, NMI, WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, AEVL, AEVH, TMIF, ADTRG, SCK32, SCK31 RXD32, RXD31 OSC1 X1 P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P93, PA0 to PA3, TCLKA, TCLKB, TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2, SCL, SDA, PB0 to PB7 Output high voltage VOH P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 P90 to P93 -IOH = 1.0 mA VCC = 2.7 to 3.6 V -IOH = 0.1 mA VCC - 0.3 -- -- VCC - 1.0 -- -- -IOH = 1.0 mA VCC = 2.7 to 3.6 V -IOH = 0.1 mA VCC - 0.3 -- -- VCC - 1.0 -- -- V VCC = 2.7 to 3.6 V -0.3 -0.3 -0.3 -0.3 -- -- -- -- 0.2VCC 0.1VCC 0.1VCC 0.2VCC Test Condition Min. -0.3 Typ. -- Max. 0.1VCC Unit V Notes Rev. 1.00 Dec. 18, 2006 Page 491 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Values Item Output low voltage Symbol VOL Applicable Pins P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 P90 to P93 IOL = 15 mA VCC = 2.7 to 3.6 V IOL = 10 mA VCC = 2.2 to 3.6 V IOL = 8.0 mA VCC = 1.8 to 3.6 V SCL, SDA VCC = 2.0 to 3.6 V IOL = 3.0 mA VCC = 1.8 to 2.0 V IOL = 3.0 mA Input/output leakage current | IIL | NMI, OSC1, X1, P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, IRQAEC, PA0 to PA3, P90 to P93 PB0 to PB7 VIN = 0.5 V to AVCC - 0.5 V Pull-up MOS current -Ip P10 to P16, P30, P36, P37, P50 to P57, P60 to P67 Input capacitance*3 CIN All input pins except f = 1 MHz, power supply pin VIN =0 V, Ta = 25C -- -- 15.0 pF VCC = 3 V, VIN = 0 V 30 -- 180 A -- -- 1.0 VIN = 0.5 V to VCC - 0.5 V -- -- 1.0 A -- -- 0.2VCC -- -- 0.4 V -- -- 0.5 -- -- 0.5 -- -- 1.0 Test Condition IOL = 0.4 mA Min. -- Typ. -- Max. 0.5 Unit V Notes Rev. 1.00 Dec. 18, 2006 Page 492 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Values Item Active mode supply current Symbol IOPE1 Applicable Pins VCC Test Condition Min. Typ. 0.7 Max. -- Unit mA Notes *1*2 Max. guideline = 1.1 x typ. Active (high-speed) mode, -- VCC = 3.0 V, fOSC = 4 MHz 2.6 -- *1*2 Max. guideline = 1.1 x typ. Active (high-speed) mode, -- VCC = 3.0 V, fOSC = 10 MHz IOPE2 VCC Active (medium-speed) mode, VCC = 1.8 V, fOSC = 2 MHz, osc/64 Active (medium-speed) mode, VCC = 3.0 V, fOSC = 4 MHz, osc/64 Active (medium-speed) mode, VCC = 3.0 V, fOSC = 10 MHz, osc/64 Sleep mode supply current ISLEEP VCC VCC= 1.8 V, fOSC= 2 MHz -- 0.3 -- mA *1*2 Max. guideline = 1.1 x typ. VCC= 3.0 V, fOSC= 4 MHz -- 1.2 -- *1*2 Max. guideline = 1.1 x typ. VCC= 3.0 V, fOSC= 10 MHz -- 3.0 5.0 *1*2 -- 0.8 1.8 *1*2 -- 0.4 -- *1*2 Max. guideline = 1.1 x typ. -- 0.2 -- mA *1*2 Max. guideline = 1.1 x typ. 6.6 10.0 *1*2 Active (high-speed) mode, -- VCC = 1.8 V, fOSC = 2 MHz Rev. 1.00 Dec. 18, 2006 Page 493 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Values Item Subactive mode supply current Symbol ISUB Applicable Pins VCC Test Condition VCC = 1.8 V, 32-kHz crystal resonator is used (SUB = w/2) VCC = 2.7 V, 32-kHz crystal resonator is used (SUB = w/8) VCC = 2.7 V, 32-kHz crystal resonator is used (SUB = w/2) Subsleep mode supply current Watch mode supply current IWATCH VCC ISUBSP VCC VCC = 2.7 V, 32-kHz crystal resonator is used (SUB = w/2) VCC = 1.8 V, Ta = 25C, 32-kHz crystal resonator not used VCC = 2.7 V, 32-kHz crystal resonator not used Standby mode ISTBY supply current VCC VCC = 1.8 V, Ta = 25C, 32-kHz crystal resonator not used VCC = 3.0 V, Ta = 25C, 32-kHz crystal resonator not used 32-kHz crystal resonator not used VCC = 3.0 V, 32KSTOP = 1 -- 0.3 -- *1*2 Reference value RAM data retaining voltage Allowable output low current (per pin) IOL Output pins except port 9 P90 to P93 -- -- 15.0 -- -- 0.5 mA VRAM VCC 1.5 -- -- V -- 1.0 5.0 *1*2 -- 0.6 -- *1*2 Reference value -- 0.4 -- A *1*2 Reference value -- 1.5 6.0 *1*2 -- 0.5 -- A *1*2 Reference value -- 4.5 10 A *1*2 -- 10.8 50 -- 4.6 -- Min. -- Typ. 5.8 Max. -- Unit A Notes *1*2 Reference value *1*2 Reference value *1*2 Rev. 1.00 Dec. 18, 2006 Page 494 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Values Item Allowable output low current (total) Allowable output high current (per pin) Allowable output high current (total) - IOH All output pins -- -- 10.0 mA VCC = 1.8 to 3.6 V -- -- 0.2 -IOH Symbol IOL Applicable Pins Output pins except port 9 Port 9 All output pins VCC = 2.7 to 3.6 V -- -- -- -- 60.0 2.0 mA Test Condition Min. -- Typ. -- Max. 20.0 Unit mA Notes Notes: 1. Pin states during current measurement. RES Mode Active (high-speed) mode (IOPE1) Active (medium-speed) mode (IOPE2) Sleep mode VCC Only on-chip timers operate On-chip WDT oscillator is off Subactive mode VCC Only CPU operates On-chip WDT oscillator is off Subsleep mode VCC Only on-chip timers operate, CPU stops On-chip WDT oscillator is off Watch mode VCC Only time base operates, CPU VCC stops On-chip WDT oscillator is off, TCSRWD1 (WDON) = 0 Standby mode VCC CPU and timers both stop On-chip WDT oscillator is off, TCSRWD1 (WDON) = 0 VCC System clock oscillator: crystal resonator Subclock oscillator: Pin X1 = GND (32KSTOP = 0) VCC VCC System clock oscillator: crystal resonator Subclock oscillator: crystal resonator VCC Pin VCC Internal State Only CPU operates On-chip WDT oscillator is off Other Pins VCC Oscillator Pins System clock oscillator: crystal resonator Subclock oscillator: Pin X1 = GND 2. Excludes current in pull-up MOS transistors and output buffers. 3. Except for the package for the TLP-85V. Rev. 1.00 Dec. 18, 2006 Page 495 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics 23.4.3 AC Characteristics Table 23.12 lists the control signal timing, table 23.13 lists the serial interface timing, and table 23.14 lists the I2C bus interface timing. Table 23.12 Control Signal Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Applicable Item System clock oscillation frequency VCC = 1.8 to 3.6 V When on-chip oscillator is selected VCC = 2.7 to 3.6 V When on-chip oscillator is selected VCC = 1.8 to 3.6 V OSC clock (OSC) cycle tOSC time VCC = 1.8 to 3.6 V 238 -- OSC1, OSC2 VCC = 2.7 to 3.6 V 100 -- 500 (1000) 500 (1000) When on-chip oscillator is selected VCC = 2.7 to 3.6 V When on-chip oscillator is selected VCC = 1.8 to 3.6 V System clock () cycle time Subclock oscillation frequency Watch clock (W) cycle tW time Subclock (SUB) cycle time Instruction cycle time 2 -- -- tcyc tsubcyc tsubcyc 2 X1, X2 -- fW X1, X2 tcyc 1 -- -- -- -- 64 64 tOSC s kHz Figure 5.7 238 -- 500 100 -- 500 *4 ns Figure 23.2 *2 2.0 -- 4.2 2.0 2.0 -- -- 4.2 10.0 *4 Symbol fOSC Pins OSC1, OSC2 Test Condition VCC = 2.7 to 3.6 V Min. 2.0 Values Typ. -- Max. 10.0 Unit MHz Reference Figure 32.768 -- or 38.4 30.5 or -- 26.0 -- 8 s Figure 23.2 tW *1 Rev. 1.00 Dec. 18, 2006 Page 496 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Applicable Item Symbol Pins OSC1, OSC2 Test Condition Crystal resonator VCC = 2.7 to 3.6 V Crystal resonator VCC = 2.2 to 3.6 V Ceramic resonator VCC = 2.2 to 3.6 V Ceramic resonator Other than above Other than above When on-chip oscillator is selected X1, X2 VCC = 2.2 to 3.6 V Other than above External clock high width X1 tCPH OSC1 VCC = 2.7 to 3.6 V VCC = 1.8 to 3.6 V -- -- 40 95 -- -- 70 -- -- -- Min. -- Values Typ. 0.8 Max. 2.0 Unit ms Reference Figure Figure 23.10 Oscillation stabilization trc time 1.2 3.0 20 45 s 80 -- -- -- 50 100 ms s *4 -- 4 -- -- 15.26 or 13.02 2.0 -- -- -- -- s Figure 5.7 ns Figure 23.2 s External clock low width tCPL OSC1 VCC = 2.7 to 3.6 V VCC = 1.8 to 3.6 V 40 95 -- -- -- 15.26 or 13.02 -- -- -- ns Figure 23.2 X1 s External clock rise time tCPr OSC1 VCC = 2.7 to 3.6 V VCC = 1.8 to 3.6 V -- -- -- -- -- -- -- -- -- -- 10 24 55.0 10 24 55.0 -- ns Figure 23.2 X1 External clock fall time tCPf OSC1 VCC = 2.7 to 3.6 V VCC = 1.8 to 3.6 V X1 RES pin low width tREL RES ns ns Figure 23.2 -- -- -- 10 ns tcyc Figure 23.3*3 Rev. 1.00 Dec. 18, 2006 Page 497 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Applicable Item Input pin high width Symbol tIH Pins IRQ0, IRQ1, NMI, IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, TMIF, ADTRG AEVL, AEVH VCC = 2.7 to 3.6 V VCC = 1.8 to 3.6 V tTCKWH TCLKA, TCLKB, Single edge TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2 Both edges specified Input pin low width tIL IRQ0, IRQ1, NMI, IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, TMIF, ADTRG AEVL, AEVH VCC = 2.7 to 3.6 V VCC = 1.8 to 3.6 V tTCKWL TCLKA, TCLKB, Single edge TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2 Both edges specified 2.5 specified 50 110 1.5 2 2.5 specified 50 110 1.5 Test Condition Min. 2 Values Typ. -- Max. -- Unit tcyc tsubcyc Reference Figure Figure 23.4 -- -- -- -- -- -- ns tcyc Figure 23.7 -- -- -- -- tcyc tsubcyc Figure 23.4 -- -- -- -- -- -- ns tcyc Figure 23.7 -- -- Notes: 1. 2. 3. 4. Selected with the SA1 and SA0 bits in the system control register 2 (SYSCR2). The value in parentheses is tOSC (max.) when an external clock is used. For details on the power-on reset characteristics, refer to table 23.16 and figure 23.1. This specification may range from the minimum value to the maximum value because of the temperature, power voltage, and dispersion of product lots. Care should be taken for the specification range in designing the system. As for actual specification, please refer to our web site. Rev. 1.00 Dec. 18, 2006 Page 498 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Table 23.13 Serial Interface Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Values Item Input clock cycle Asynchronous Clocked synchronous Input clock pulse width Transmit data delay time (clocked synchronous) Receive data setup time (clocked synchronous) VCC = 2.7 to 3.6 V Receive data hold time (clocked synchronous) tRXH VCC = 2.7 to 3.6 V 100 238 100 -- -- ns Figure 23.6 tRXS 238 -- -- ns Figure 23.6 tSCKW tTXD 0.4 -- -- -- 0.6 1 tscyc tcyc or tsubcyc Figure 23.5 Figure 23.6 Symbol tscyc Test Condition Min. 4 6 Typ. -- -- Max. -- -- Unit tcyc or tsubcyc Reference Figure Figure 23.5 Rev. 1.00 Dec. 18, 2006 Page 499 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Table 23.14 I2C Bus Interface Timing VCC = 1.8 V to 3.6 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise specified. Test Condition Values Min. 12tcyc + 600 3tcyc + 300 5tcyc + 300 -- -- Typ. -- -- -- -- -- Max. -- -- -- 300 1tcyc -- Unit ns ns ns ns ns Reference Figure Figure 23.8 Item SCL input cycle time SCL input high width SCL input low width Symbol tSCL tSCLH tSCLL SCL and SDA input fall time tSf SCL and SDA input spike pulse removal time SDA input bus-free time Start condition input hold time Retransmission start condition input setup time tSP tBUF tSTAH tSTAS 5tcyc 3tcyc 3tcyc 3tcyc 1tcyc + 20 0 0 -- ns -- -- ns -- -- ns Setup time for stop condition tSTOS input Data-input setup time Data-input hold time Capacitive load of SCL and SDA SCL and SDA output fall time tSDAS tSDAH Cb -- -- ns -- -- -- -- -- 400 ns ns pF tSf -- -- 300 ns Rev. 1.00 Dec. 18, 2006 Page 500 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics 23.4.4 A/D Converter Characteristics Table 23.15 lists the A/D converter characteristics. Table 23.15 A/D Converter Characteristics VCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified. Applicable Item Analog power supply voltage Analog input voltage AVIN AN0 to AN7 -0.3 -- AVCC + 0.3 Analog power supply current AIOPE AISTOP1 AVCC AVCC AVCC = 3.0 V -- -- -- 600 1.0 -- mA A *2 Reference value AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) Nonlinearity error AVCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V AVCC = 2.0 V to 3.6 V VCC = 2.0 V to 3.6 V Other than above Quantization error Absolute accuracy AVCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V AVCC = 2.0 V to 3.6 V VCC = 2.0 V to 3.6 V Other than above -- -- 8.0 *4 -- -- 6.0 -- -- -- -- -- -- 7.5 0.5 4.0 LSB LSB *4 -- -- 5.5 -- -- 3.5 LSB -- -- 10 bits RAIN -- -- 10.0 k CAIN AVCC AN0 to AN7 -- -- -- -- 5 15.0 A pF *3 V Symbol AVCC Pins AVCC Test Condition Min. 1.8 Values Typ. -- Max. 3.6 Unit V Notes *1 Rev. 1.00 Dec. 18, 2006 Page 501 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics Applicable Item Conversion time Symbol Pins Test Condition AVCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V AVCC = 2.0 V to 3.6 V VCC = 2.0 V to 3.6 V Other than above Values Min. 6.2 Typ. -- Max. 124 Unit s Notes 14.7 -- 124 31 -- 124 Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at a reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle. 4. Conversion time = 62 s Rev. 1.00 Dec. 18, 2006 Page 502 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics 23.4.5 Power-On Reset Circuit Characteristics Table 23.16 lists the power-on reset circuit characteristics. Table 23.16 Power-On Reset Circuit Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications), unless otherwise specified. Values Item Reset voltage Power supply rise time Symbol V_rst t_vtr Test Condition Min. 0.7Vcc Typ. 0.8Vcc Max. 0.9Vcc Unit V Notes The Vcc rise time should be shorter than half the RES rise time. Reset count time Count start time t_out t_cr 0.8 -- 4.0 s Adjustable by the value of the external capacitor of the RES pin. On-chip pull-up resistance Rp Vcc = 3.0 V 60 100 -- k t_vtr Vcc t_vtr x 2 RES V_rst Internal reset signal t_cr t_out (eight states) Figure 23.1 Power-On Reset Circuit Reset Timing Rev. 1.00 Dec. 18, 2006 Page 503 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics 23.4.6 Watchdog Timer Characteristics Table 23.17 Watchdog Timer Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications), unless otherwise specified. Applicable Item On-chip oscillator overflow time Symbol tovf Pins Test Condition Min. 0.2 Values Typ. 0.4 Max. -- Unit s Notes 23.5 Operation Timing Figures 23.2 to 23.7 show operation timings. t OSC, tw V IH OSC1 x1 V IL t CPH t CPr t CPL t CPf Figure 23.2 Clock Input Timing RES V IL t REL Figure 23.3 RES Low Width Timing Rev. 1.00 Dec. 18, 2006 Page 504 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics NMI, IRQ0, IRQ1, IRQ3, IRQ4,TMIF, ADTRG, WKP0 to WKP7, IRQAEC, AEVL, AEVH V IL V IH t IL t IH Figure 23.4 Input Timing t SCKW SCK31 SCK32 t scyc Figure 23.5 SCK3 Input Clock Timing Rev. 1.00 Dec. 18, 2006 Page 505 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics t scyc VIH or VOH* VIL or VOL* t TXD SCK31 SCK32 TXD31 TXD32 (transmit data) VOH* VOL* t RXS t RXH RXD31 RXD32 (receive data) Note: * Output timing reference levels Output high Output low VOH = 1/2 Vcc + 0.2 V VOL = 0.8 V Load conditions are shown in figure 23.9. Figure 23.6 SCI3 Input/Output Timing in Clocked Synchronous Mode TCLKA to TCLKC tTCKWL tTCKWH Figure 23.7 Clock Input Timing for TCLKA to TCLKC Pins Rev. 1.00 Dec. 18, 2006 Page 506 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics SDA tBUF VIH VIL tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf tSCLL tSCL Sr* tSr tSDAH tSDAS P* Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 23.8 I2C Bus Interface Input/Output Timing 23.6 Output Load Circuit VCC 2.4 k LSI output pin 30 pF 12 k Figure 23.9 Output Load Condition Rev. 1.00 Dec. 18, 2006 Page 507 of 568 REJ09B0348-0100 Section 23 Electrical Characteristics 23.7 Recommended Resonators Table 23.18 Recommended Crystal Resonators Frequency (MHz) 4.194 10 Manufacturer KYOCERA KINSEKI Corporation KYOCERA KINSEKI Corporation Product Type HC-49/V-S HC-49/V-S Table 23.19 Recommended Ceramic Resonators Frequency (MHz) 2 Manufacturer Murata Manufacturing Co., Ltd. Murata Manufacturing Co., Ltd. 4.194 Murata Manufacturing Co., Ltd. Murata Manufacturing Co., Ltd. 10 Murata Manufacturing Co., Ltd. Murata Manufacturing Co., Ltd. Product Type CSTCC2M00G53-B0 CSTCC2M00G56-B0 CSTLS4M19G53-B0 CSTLS4M19G56-B0 CSTLS10M0G53-B0 CSTLS10M0G56-B0 23.8 Usage Note The F-ZTAT and masked ROM versions satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on. When system evaluation testing is carried out using the F-ZTAT version, the same evaluation testing should also be conducted for the masked ROM version when changing over to that version. Rev. 1.00 Dec. 18, 2006 Page 508 of 568 REJ09B0348-0100 Appendix Appendix A. A.1 Instruction Set Instruction List Condition Code Symbol Rd Rs Rn ERd ERs ERn (EAd) (EAs) PC SP CCR N Z V C disp + - x / Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) Destination operand Source operand Program counter Stack pointer Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Displacement Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the right Logical AND of the operands on both sides Logical OR of the operands on both sides Logical exclusive OR of the operands on both sides Rev. 1.00 Dec. 18, 2006 Page 509 of 568 REJ09B0348-0100 Appendix Symbol ( ), < > Description NOT (logical complement) Contents of operand Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). Condition Code Notation (cont) Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 Not affected by execution of the instruction Varies depending on conditions, described in notes * 0 1 -- Rev. 1.00 Dec. 18, 2006 Page 510 of 568 REJ09B0348-0100 Appendix Table A.1 Instruction Set 1. Data Transfer Instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size Condition Code No. of States*1 @(d, ERn) I H N Z V C MOV MOV.B #xx:8, Rd B B B B B B 2 2 2 4 8 2 ---- ---- ---- ---- ---- ---- #xx:8 Rd8 Rs8 Rd8 @ERs Rd8 @(d:16, ERs) Rd8 @(d:24, ERs) Rd8 @ERs Rd8 ERs32+1 ERs32 2 4 6 2 4 8 2 @aa:8 Rd8 @aa:16 Rd8 @aa:24 Rd8 Rs8 @ERd Rs8 @(d:16, ERd) Rs8 @(d:24, ERd) ERd32-1 ERd32 Rs8 @ERd 2 4 6 Rs8 @aa:8 Rs8 @aa:16 Rs8 @aa:24 #xx:16 Rd16 2 2 4 8 2 Rs16 Rd16 @ERs Rd16 @(d:16, ERs) Rd16 @(d:24, ERs) Rd16 @ERs Rd16 ERs32+2 @ERd32 4 6 2 4 8 @aa:16 Rd16 @aa:24 Rd16 Rs16 @ERd Rs16 @(d:16, ERd) Rs16 @(d:24, ERd) 0-- 0-- 0-- 0-- 0-- 0-- 2 2 4 6 10 6 MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd B B B B B B B ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 4 6 8 4 6 10 6 MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd B B B W4 W W ---- ---- ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 4 6 8 4 2 4 6 10 6 MOV.W @(d:16, ERs), Rd W MOV.W @(d:24, ERs), Rd W MOV.W @ERs+, Rd W MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd W W W ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 6 8 4 6 10 MOV.W Rs, @(d:16, ERd) W MOV.W Rs, @(d:24, ERd) W Rev. 1.00 Dec. 18, 2006 Page 511 of 568 REJ09B0348-0100 Advanced Mnemonic Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size Condition Code No. of States*1 @(d, ERn) I H N Z V C MOV MOV.W Rs, @-ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, Rd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd W 2 ERd32-2 ERd32 Rs16 @ERd 4 6 Rs16 @aa:16 Rs16 @aa:24 #xx:32 Rd32 ERs32 ERd32 ---- 0-- 6 W W L L L L L L 6 2 4 6 10 4 ---- ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 6 8 6 2 8 10 14 10 @ERs ERd32 @(d:16, ERs) ERd32 @(d:24, ERs) ERd32 @ERs ERd32 ERs32+4 ERs32 6 8 @aa:16 ERd32 @aa:24 ERd32 ERs32 @ERd 6 10 4 ERs32 @(d:16, ERd) ERs32 @(d:24, ERd) ERd32-4 ERd32 ERs32 @ERd 6 8 ERs32 @aa:16 ERs32 @aa:24 2 @SP Rn16 SP+2 SP 4 @SP ERn32 SP+4 SP 2 SP-2 SP Rn16 @SP 4 SP-4 SP ERn32 @SP 4 Cannot be used in this LSI Cannot be used in this LSI MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @-ERd L L L L L L 4 ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 10 12 8 10 14 10 MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 POP POP.W Rn POP.L ERn L L W ---- ---- ---- 0-- 0-- 0-- 10 12 6 L ---- 0-- 10 PUSH PUSH.W Rn PUSH.L ERn W ---- 0-- 6 L ---- 0-- 10 MOVFPE MOVFPE @aa:16, Rd B Cannot be used in this LSI Cannot be used in this LSI MOVTPE MOVTPE Rs, @aa:16 B 4 Rev. 1.00 Dec. 18, 2006 Page 512 of 568 REJ09B0348-0100 Advanced Mnemonic Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix 2. Arithmetic Instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size Condition Code No. of States*1 @(d, ERn) I H N Z V C ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd B B 2 2 -- -- Rd8+#xx:8 Rd8 Rd8+Rs8 Rd8 Rd16+#xx:16 Rd16 2 Rd16+Rs16 Rd16 ERd32+#xx:32 ERd32 2 ERd32+ERs32 ERd32 Rd8+#xx:8 +C Rd8 2 2 2 2 2 2 2 2 2 2 Rd8+Rs8 +C Rd8 ERd32+1 ERd32 ERd32+2 ERd32 ERd32+4 ERd32 Rd8+1 Rd8 Rd16+1 Rd16 Rd16+2 Rd16 ERd32+1 ERd32 ERd32+2 ERd32 Rd8 decimal adjust Rd8 Rd8-Rs8 Rd8 Rd16-#xx:16 Rd16 2 Rd16-Rs16 Rd16 2 2 4 2 6 W4 W L 6 -- (1) -- (1) -- (2) ADD.L ERs, ERd L -- (2) 2 ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS ADDS.L #1, ERd ADDS.L #2, ERd ADDS.L #4, ERd INC INC.B Rd INC.W #1, Rd INC.W #2, Rd INC.L #1, ERd INC.L #2, ERd DAA SUB DAA Rd B B L L L B W W L L B 2 -- -- (3) (3) 2 2 2 2 2 2 2 2 2 2 2 ------------ ------------ ------------ ---- ---- ---- ---- ---- --* -- -- -- -- -- *-- SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd B W4 W L L B B L L L B W W 2 6 2 -- 2 4 2 6 2 2 2 2 2 2 2 2 2 -- (1) -- (1) ERd32-#xx:32 ERd32 -- (2) 2 ERd32-ERs32 ERd32 -- (2) SUBX SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS SUBS.L #1, ERd SUBS.L #2, ERd SUBS.L #4, ERd DEC DEC.B Rd DEC.W #1, Rd DEC.W #2, Rd Rd8-#xx:8-C Rd8 2 2 2 2 2 2 2 Rd8-Rs8-C Rd8 ERd32-1 ERd32 ERd32-2 ERd32 ERd32-4 ERd32 Rd8-1 Rd8 Rd16-1 Rd16 Rd16-2 Rd16 -- -- (3) (3) ------------ ------------ ------------ ---- ---- ---- -- -- -- Rev. 1.00 Dec. 18, 2006 Page 513 of 568 REJ09B0348-0100 Advanced Mnemonic Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size Condition Code No. of States*1 @(d, ERn) I H N Z V C DEC DEC.L #1, ERd DEC.L #2, ERd DAS DAS.Rd L L B 2 2 2 ---- ---- --* ERd32-1 ERd32 ERd32-2 ERd32 Rd8 decimal adjust Rd8 Rd8 x Rs8 Rd16 (unsigned multiplication) Rd16 x Rs16 ERd32 (unsigned multiplication) Rd8 x Rs8 Rd16 (signed multiplication) Rd16 x Rs16 ERd32 (signed multiplication) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (unsigned division) ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (unsigned division) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (signed division) ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (signed division) Rd8-#xx:8 -- -- 2 2 2 *-- MULXU MULXU. B Rs, Rd B 2 ------------ 14 MULXU. W Rs, ERd W 2 ------------ 22 MULXS MULXS. B Rs, Rd B 4 ---- ---- 16 MULXS. W Rs, ERd W 4 ---- ---- 24 DIVXU DIVXU. B Rs, Rd B 2 -- -- (6) (7) -- -- 14 DIVXU. W Rs, ERd W 2 -- -- (6) (7) -- -- 22 DIVXS DIVXS. B Rs, Rd B 4 -- -- (8) (7) -- -- 16 DIVXS. W Rs, ERd W 4 -- -- (8) (7) -- -- 24 CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd B B 2 2 -- -- 2 2 4 2 4 2 Rd8-Rs8 Rd16-#xx:16 W4 W L L 6 2 2 -- (1) -- (1) -- (2) -- (2) Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32 Rev. 1.00 Dec. 18, 2006 Page 514 of 568 REJ09B0348-0100 Advanced Mnemonic Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix Addressing Mode and Instruction Length (bytes) No. of States*1 Condition Code @(d, ERn) I H N Z V C NEG NEG.B Rd NEG.W Rd NEG.L ERd EXTU EXTU.W Rd EXTU.L ERd B W L W 2 2 2 2 -- -- -- 0-Rd8 Rd8 0-Rd16 Rd16 0-ERd32 ERd32 0 ( 2 2 2 2 ---- 0 0-- L 2 ---- 0 0-- 2 EXTS EXTS.W Rd W 2 ---- 0-- 2 EXTS.L ERd L 2 ---- 0-- 2 Rev. 1.00 Dec. 18, 2006 Page 515 of 568 REJ09B0348-0100 Advanced Mnemonic @-ERn/@ERn+ Operand Size Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix 3. Logic Instructions Addressing Mode and Instruction Length (bytes) No. of States*1 Condition Code @(d, ERn) I H N Z V C AND AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd B B 2 2 ---- ---- ---- ---- Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 2 Rd16Rs16 Rd16 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 W4 W L L B B W4 W L L B B W4 W L L B W L 6 4 2 2 2 2 2 2 6 4 2 2 2 6 4 ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- OR OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8 Rd8 Rd16 Rd16 Rd32 Rd32 ---- ---- ---- NOT NOT.B Rd NOT.W Rd NOT.L ERd Rev. 1.00 Dec. 18, 2006 Page 516 of 568 REJ09B0348-0100 Advanced Mnemonic @-ERn/@ERn+ Operand Size Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix 4. Shift Instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size Condition Code No. of States*1 @(d, ERn) I H N Z V C SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd ROTXL ROTXL.B Rd B W L B W L B W L B W L B W L B W L B W L B W L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C MSB LSB C MSB C MSB 0 MSB C MSB LSB C MSB C MSB LSB LSB LSB LSB LSB 0 ---- ---- ---- ---- ---- ---- ---- 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ---- ---- ---- C ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ROTXL.W Rd ROTXL.L ERd ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd C MSB LSB ---- ---- Rev. 1.00 Dec. 18, 2006 Page 517 of 568 REJ09B0348-0100 Advanced Mnemonic Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix 5. Bit-Manipulation Instructions Addressing Mode and Instruction Length (bytes) No. of States*1 Condition Code @(d, ERn) I H N Z V C BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BNOT BNOT #xx:3, Rd B B B B B B B B B B B B B 2 4 4 2 4 4 2 4 4 2 4 4 2 (#xx:3 of Rd8) 1 (#xx:3 of @ERd) 1 (#xx:3 of @aa:8) 1 (Rn8 of Rd8) 1 (Rn8 of @ERd) 1 (Rn8 of @aa:8) 1 (#xx:3 of Rd8) 0 (#xx:3 of @ERd) 0 (#xx:3 of @aa:8) 0 (Rn8 of Rd8) 0 (Rn8 of @ERd) 0 (Rn8 of @aa:8) 0 (#xx:3 of Rd8) (#xx:3 of Rd8) 4 (#xx:3 of @ERd) (#xx:3 of @ERd) 4 (#xx:3 of @aa:8) (#xx:3 of @aa:8) (Rn8 of Rd8) (Rn8 of Rd8) 4 (Rn8 of @ERd) (Rn8 of @ERd) 4 (Rn8 of @aa:8) (Rn8 of @aa:8) (#xx:3 of Rd8) Z 4 4 (#xx:3 of @ERd) Z (#xx:3 of @aa:8) Z (Rn8 of @Rd8) Z 4 4 (Rn8 of @ERd) Z (Rn8 of @aa:8) Z (#xx:3 of Rd8) C ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 2 8 8 2 8 8 2 8 8 2 8 8 2 BNOT #xx:3, @ERd B ------------ 8 BNOT #xx:3, @aa:8 B ------------ 8 BNOT Rn, Rd B 2 ------------ 2 BNOT Rn, @ERd B ------------ 8 BNOT Rn, @aa:8 B ------------ 8 BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BLD B B B B B B B 2 ------ ------ ------ ------ ------ ------ ---- ---- ---- ---- ---- ---- 2 6 6 2 6 6 2 2 BLD #xx:3, Rd 2 ---------- Rev. 1.00 Dec. 18, 2006 Page 518 of 568 REJ09B0348-0100 Advanced Mnemonic @-ERn/@ERn+ Operand Size Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size Condition Code No. of States*1 @(d, ERn) I H N Z V C BLD BLD #xx:3, @ERd BLD #xx:3, @aa:8 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 2 2 2 2 2 2 2 2 2 4 4 ---------- ---------- ---------- ---------- ---------- (#xx:3 of @ERd) C (#xx:3 of @aa:8) C (#xx:3 of Rd8) C (#xx:3 of @ERd) C 4 (#xx:3 of @aa:8) C C (#xx:3 of Rd8) C (#xx:3 of @ERd24) 4 C (#xx:3 of @aa:8) C (#xx:3 of Rd8) C (#xx:3 of @ERd24) 4 C (#xx:3 of @aa:8) C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 BILD BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BAND BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 4 ------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- 4 4 4 4 4 C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C ---------- ---------- ---------- ---------- ---------- 4 4 4 C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C ---------- ---------- ---------- ---------- ---------- 4 4 4 C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C ---------- Rev. 1.00 Dec. 18, 2006 Page 519 of 568 REJ09B0348-0100 Advanced Mnemonic Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix 6. Branching Instructions Addressing Mode and Instruction Length (bytes) No. of States*1 Condition Code @(d, ERn) Branch Condition If condition Always is true then PC PC+d Never else next; C Z = 0 I H N Z V C Bcc BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 ------------ ------------ ------------ ------------ ------------ ------------ 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 C Z = 1 ------------ ------------ C=0 ------------ ------------ C=1 ------------ ------------ Z=0 ------------ ------------ Z=1 ------------ ------------ V=0 ------------ ------------ V=1 ------------ ------------ N=0 ------------ ------------ N=1 ------------ ------------ NV = 0 ------------ ------------ NV = 1 ------------ ------------ Z (NV) = 0 -- -- -- -- -- -- ------------ Z (NV) = 1 -- -- -- -- -- -- ------------ Rev. 1.00 Dec. 18, 2006 Page 520 of 568 REJ09B0348-0100 Advanced Mnemonic @-ERn/@ERn+ Operand Size Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix Addressing Mode and Instruction Length (bytes) No. of States*1 Condition Code @(d, ERn) I H N Z V C JMP JMP @ERn JMP @aa:24 JMP @@aa:8 -- -- -- -- 2 4 2 2 PC ERn PC aa:24 PC @aa:8 PC @-SP PC PC+d:8 PC @-SP PC PC+d:16 PC @-SP PC ERn 4 PC @-SP PC aa:24 2 PC @-SP PC @aa:8 2 PC @SP+ ------------ ------------ ------------ ------------ 8 6 4 6 10 8 BSR BSR d:8 BSR d:16 JSR -- 4 ------------ 8 10 JSR @ERn -- 2 ------------ 6 JSR @aa:24 -- ------------ 8 10 JSR @@aa:8 -- ------------ 8 12 RTS RTS -- ------------ 8 10 Rev. 1.00 Dec. 18, 2006 Page 521 of 568 REJ09B0348-0100 Advanced 8 Mnemonic @-ERn/@ERn+ Operand Size Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix 7. System Control Instructions Addressing Mode and Instruction Length (bytes) No. of States*1 Condition Code @(d, ERn) I H N Z V C RTE RTE -- CCR @SP+ PC @SP+ Transition to powerdown state 10 SLEEP SLEEP -- 2 2 4 6 10 4 2 LDC LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR B B W W W W #xx:8 CCR Rs8 CCR @ERs CCR @(d:16, ERs) CCR @(d:24, ERs) CCR @ERs CCR ERs32+2 ERs32 6 8 2 4 6 10 4 @aa:16 CCR @aa:24 CCR CCR Rd8 CCR @ERd CCR @(d:16, ERd) CCR @(d:24, ERd) ERd32-2 ERd32 CCR @ERd 6 8 CCR @aa:16 CCR @aa:24 2 2 6 8 12 8 LDC @aa:16, CCR LDC @aa:24, CCR STC STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @-ERd W W B W W W W 8 10 2 6 8 12 8 STC CCR, @aa:16 STC CCR, @aa:24 ANDC ANDC #xx:8, CCR ORC NOP W W B B B -- 2 2 2 8 10 CCR#xx:8 CCR CCR#xx:8 CCR CCR#xx:8 CCR 2 PC PC+2 2 2 2 2 ORC #xx:8, CCR XORC XORC #xx:8, CCR NOP Rev. 1.00 Dec. 18, 2006 Page 522 of 568 REJ09B0348-0100 Advanced Mnemonic @-ERn/@ERn+ Operand Size Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix 8. Block Transfer Instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ Operand Size Condition Code No. of States*1 @(d, ERn) I H N Z V C EEPMOV EEPMOV. B -- 4 if R4L 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L until R4L=0 else next 4 if R4 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4-1 R4 until R4=0 else next -- -- -- -- -- -- 8+ 4n*2 EEPMOV. W -- -- -- -- -- -- -- 8+ 4n*2 Notes: 1. The number of states in cases where the instruction code and its operands are located in on-chip memory is shown here. For other cases, see appendix A.3, Number of Execution States. 2. n is the value set in register R4L or R4. (1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) Retains its previous value when the result is zero; otherwise cleared to 0. (4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. (6) Set to 1 when the divisor is negative; otherwise cleared to 0. (7) Set to 1 when the divisor is zero; otherwise cleared to 0. (8) Set to 1 when the quotient is negative; otherwise cleared to 0. Rev. 1.00 Dec. 18, 2006 Page 523 of 568 REJ09B0348-0100 Advanced Mnemonic Operation @(d, PC) Normal @@aa @ERn @aa #xx Rn -- Appendix A.2 Operation Code Map Operation Code Map (1) Table A.2 Rev. 1.00 Dec. 18, 2006 Page 524 of 568 REJ09B0348-0100 Instruction code: 1st byte 2nd byte AH AL BH BL Instruction when most significant bit of BH is 0. Instruction when most significant bit of BH is 1. 4 5 XORC ADD SUB Table A-2 Table A-2 (2) (2) CMP AL 2 STC OR.B XOR.B AND.B Table A-2 (2) AH LDC ORC ANDC LDC Table A-2 Table A-2 (2) (2) MOV 0 1 3 6 7 8 9 A B C D E ADDX SUBX F Table A-2 (2) Table A-2 (2) 0 NOP Table A-2 (2) 1 Table A-2 Table A-2 Table A-2 Table A-2 (2) (2) (2) (2) 2 MOV.B 3 BHI MULXU BST OR BCLR BOR MOV BIOR ADD ADDX CMP SUBX OR XOR AND 4 DIVXU XOR BXOR BIXOR BIAND BILD BAND BIST BLD AND RTS BSR RTE TRAPA Table A-2 (2) BRA JMP BRN BLS BCC BCS BNE BEQ BPL BVC BVS BMI BGE BSR BLT BGT JSR MOV BLE 5 MULXU DIVXU 6 BTST BSET BNOT 7 Table A-2 Table A-2 EEPMOV (2) (2) Table A-2 (3) 8 9 A B C D E Appendix Rev. 1.00 Dec. 18, 2006 Page 525 of 568 REJ09B0348-0100 F MOV Appendix Table A.2 REJ09B0348-0100 3 LDC/STC SLEEP ADD INC ADDS Instruction code: 1st byte 2nd byte AH AL BH BL 4 Table A-2 Table A-2 (3) (3) BH AH AL 5 6 7 8 9 A B C D E 0 1 2 F Table A-2 (3) 01 MOV 0A INC INC Rev. 1.00 Dec. 18, 2006 Page 526 of 568 INC INC 0B MOV SHLL SHAL SHAR ROTL ROTR SHAL SHAR ROTL ROTR NEG ADDS Operation Code Map (2) 0F DAA 10 SHLR ROTXL ROTXR NOT EXTU EXTU NEG SHLL 11 SHLR 12 ROTXL 13 ROTXR 17 NOT EXTS EXTS 1A DEC DEC DEC SUB SUB DEC DEC 1B SUBS 1F BLS DAS BCC OR OR XOR XOR BCS BNE AND AND BEQ CMP 58 SUB SUB BRA BRN BHI BVC BVS BPL BMI BGE BLT BGT BLE 79 MOV ADD CMP 7A MOV ADD CMP Table A.2 Instruction code: 1st byte 2nd byte 3rd byte 4th byte AH AL BH BL CH CL DH DL Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. CL 3 4 5 6 7 8 9 A B C D E F AH ALBH BLCH LDC STC STC LDC LDC STC 0 1 2 01406 LDC STC Operation Code Map (3) 01C05 DIVXS OR BTST BOR BTST BIOR BIST BIXOR BIAND BILD BST BXOR BAND BLD XOR AND MULXS MULXS 01D05 DIVXS 01F06 7Cr06 * 1 7Cr07 * 1 7Dr06 * 1 BSET BNOT BCLR 7Dr07 * 1 BTST BOR BTST BIOR BIXOR BIAND BILD BST BIST BXOR BAND BLD BSET BNOT BCLR 7Eaa6 * 2 7Eaa7 * 2 7Faa6 * 2 BSET BNOT BCLR 7Faa7 * 2 BSET BNOT BCLR Notes: 1. r is the register designation field. 2. aa is the absolute address field. Appendix Rev. 1.00 Dec. 18, 2006 Page 527 of 568 REJ09B0348-0100 Appendix A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle. The total number of states required for execution of an instruction can be calculated by the following expression: Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. BSET #0, @FF00 From table A.4: I = L = 2, J = K = M = N= 0 From table A.3: SI = 2, SL = 2 Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area. JSR @@ 30 From table A.4: I = 2, J = K = 1, From table A.3: SI = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2+ 1 x 2 = 8 L=M=N=0 Rev. 1.00 Dec. 18, 2006 Page 528 of 568 REJ09B0348-0100 Appendix Table A.3 Number of Cycles in Each Instruction Access Location On-Chip Memory SI SJ SK SL SM SN 2 or 3* -- 1 2 On-Chip Peripheral Module -- Execution Status (Instruction Cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation Note: * Depends on which on-chip peripheral module is accessed. See section 22.1, Register Addresses (Address Order). Rev. 1.00 Dec. 18, 2006 Page 529 of 568 REJ09B0348-0100 Appendix Table A.4 Number of Cycles in Each Instruction Instruction Fetch I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 Stack Branch Addr. Read Operation K J Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDX ADDS #1/2/4, ERd ADDX #xx:8, Rd ADDX Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 Rev. 1.00 Dec. 18, 2006 Page 530 of 568 REJ09B0348-0100 Appendix Instruction Fetch I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic Bcc BLT d:8 BGT d:8 BLE d:8 BRA d:16(BT d:16) BRN d:16(BF d:16) BHI d:16 BLS d:16 BCC d:16(BHS d:16) BCS d:16(BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 Rev. 1.00 Dec. 18, 2006 Page 531 of 568 REJ09B0348-0100 Appendix Instruction Fetch I 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 1 2 2 2 2 1 1 2 2 2 2 2 1 1 2 2 2 2 1 1 1 1 2 2 1 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic BIOR BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BLD BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BSR BSR d:8 BSR d:16 BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 Rev. 1.00 Dec. 18, 2006 Page 532 of 568 REJ09B0348-0100 Appendix Instruction Fetch I 1 2 2 1 2 2 1 2 2 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 2 2 1 1 1 1 2n+2*1 2n+2*1 12 20 12 20 1 1 1 1 1 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DUVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd EEPMOV EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd Rev. 1.00 Dec. 18, 2006 Page 533 of 568 REJ09B0348-0100 Appendix Instruction Fetch I 1 1 1 2 2 2 2 2 2 1 1 2 3 5 2 3 4 1 1 1 2 4 1 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 2 1 1 1 1 1 2 2 2 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic INC INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR LDC@ERs, CCR LDC@(d:16, ERs), CCR LDC@(d:24,ERs), CCR LDC@ERs+, CCR LDC@aa:16, CCR LDC@aa:24, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @Erd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd MOV.B Rs, @aa:8 Rev. 1.00 Dec. 18, 2006 Page 534 of 568 REJ09B0348-0100 Appendix Instruction Fetch I 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 2 Instruction Mnemonic MOV MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16,ERs), Rd MOV.W @(d:24,ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16,ERd) MOV.W Rs, @(d:24,ERd) MOV MOV.W Rs, @-ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16,ERs), ERd MOV.L @(d:24,ERs), ERd MOV.L @ERs+, ERd MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs,@ERd MOV.L ERs, @(d:16,ERd) MOV.L ERs, @(d:24,ERd) MOV.L ERs, @-ERd MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 MOVFPE MOVTPE MOVFPE @aa:16, Rd* MOVTPE Rs,@aa:16*2 Branch Stack Addr. Read Operation J K Byte Data Access L 1 1 Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2 2 2 Rev. 1.00 Dec. 18, 2006 Page 535 of 568 REJ09B0348-0100 Appendix Instruction Fetch I 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 2 1 2 2 2 2 2 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N 12 20 12 20 Instruction Mnemonic MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd ORC POP ORC #xx:8, CCR POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd Rev. 1.00 Dec. 18, 2006 Page 536 of 568 REJ09B0348-0100 Appendix Instruction Fetch I 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 5 2 3 4 1 2 1 3 1 1 1 1 1 1 1 1 2 2 1 2 2 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd RTE RTS SHAL RTE RTS SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP STC SLEEP STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16,ERd) STC CCR, @(d:24,ERd) STC CCR,@-ERd STC CCR, @aa:16 STC CCR, @aa:24 SUB SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd SUBS SUBS #1/2/4, ERd Rev. 1.00 Dec. 18, 2006 Page 537 of 568 REJ09B0348-0100 Appendix Instruction Fetch I 1 1 1 1 2 1 3 2 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N Instruction Mnemonic SUBX SUBX #xx:8, Rd SUBX. Rs, Rd XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC XORC #xx:8, CCR Notes: 1. n: Specified value in R4L. The source and destination operands are accessed n+1 times respectively. 2. It can not be used in this LSI. Rev. 1.00 Dec. 18, 2006 Page 538 of 568 REJ09B0348-0100 Appendix A.4 Combinations of Instructions and Addressing Modes Combinations of Instructions and Addressing Modes Addressing Mode @ERn+/@ERn @(d:16.ERn) @(d:24.ERn) @(d:16.PC) Table A.5 @@aa:8 Functions Instructions @ERn #xx @(d:8.PC) @aa:16 @aa:24 @aa:8 Rn Data MOV transfer POP, PUSH instructions MOVFPE, MOVTPE Arithmetic operations ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, MULXS, DIVXU, DIVXS NEG EXTU, EXTS Logical AND, OR, XOR operations NOT Shift operations Bit manipulations Branching BCC, BSR instructions JMP, JSR RTS System RTE control SLEEP instructions LDC STC ANDC, ORC, XORC NOP Block data transfer instructions BWL BWL BWL BWL BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- BWL BWL WL BWL B B -- L -- BWL -- -- B BW -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- WL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- B -- -- BWL WL BWL BWL BWL B -- -- -- -- -- B B -- -- -- -- -- -- -- -- B -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BW Rev. 1.00 Dec. 18, 2006 Page 539 of 568 REJ09B0348-0100 -- Appendix B. B.1 I/O Ports I/O Port Block Diagrams SBY (Low at a reset or in standby mode) PUCR16 VCC VCC Internal data bus P16 PDR16 VSS PCR16 SCI4 module SCKO4 SCKI4 SCKIE SCKOE PDR1: PCR1: Port data register 1 Port control register 1 PUCR1: Port pull-up control register 1 Figure B.1 (a) Port 1 Block Diagram (P16) (F-ZTAT Version) Rev. 1.00 Dec. 18, 2006 Page 540 of 568 REJ09B0348-0100 Appendix SBY PUCR16 VCC VCC PDR16 P16 PCR16 VSS PDR1: PCR1: Port data register 1 Port control register 1 PUCR1: Port pull-up control register 1 Figure B.1 (b) Port 1 Block Diagram (P16) (Masked ROM Version) SBY PUCR1n TPU module TO1AE (P12) TO1BE (P13) TO2AE (P14) TO2BE (P15) VCC VCC Internal data bus P1n PDR1n TO1A (P12) TO1B (P13) TO2A (P14) TO2B (P15) TI1A (P12) TI1B (P13) TI2A (P14) TI2B (P15) VSS PCR1n PDR1: Port data register 1 PCR1: Port control register 1 PUCR1: Port pull-up control register 1 n = 5 to 2 TCLKA (P12) TCLKB (P13) TCLKC (P14) Figure B.1 (c) Port 1 Block Diagram (P15 to P12) Rev. 1.00 Dec. 18, 2006 Page 541 of 568 REJ09B0348-0100 Internal data bus Appendix SBY PUCR1n VCC VCC PMR1n Internal data bus P1n PDR1n VSS PCR1n AEC module AEVH(P10) AEVL(P11) PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 n = 1, 0 Figure B.1 (d) Port 1 Block Diagram (P11, P10) Rev. 1.00 Dec. 18, 2006 Page 542 of 568 REJ09B0348-0100 Appendix SBY PUCR37 VCC VCC Internal data bus P37 PDR37 VSS PCR37 SCI4 module SO4 TE4 PDR3: PCR3: Port data register 3 Port control register 3 PUCR3: Port pull-up control register 3 Figure B.2 (a) Port 3 Block Diagram (P37) (F-ZTAT Version) SBY PUCR37 VCC VCC PDR37 P37 PCR37 VSS PDR3: PCR3: Port data register 3 Port control register 3 PUCR3: Port pull-up control register 3 Figure B.2 (b) Port 3 Block Diagram (P37) (Masked ROM Version) Rev. 1.00 Dec. 18, 2006 Page 543 of 568 REJ09B0348-0100 Internal data bus Appendix SBY PUCR36 VCC VCC Internal data bus P36 PDR36 VSS PCR36 SCI4 module SI RE PDR3: PCR3: Port data register 3 Port control register 3 PUCR3: Port pull-up control register 3 Figure B.2 (c) Port 3 Block Diagram (P36) (F-ZTAT Version) SBY PUCR36 VCC VCC Internal data bus PDR36 P36 PCR36 VSS PDR3: PCR3: Port data register 3 Port control register 3 PUCR3: Port pull-up control register 3 Figure B.2 (d) Port 3 Block Diagram (P36) (Masked ROM Version) Rev. 1.00 Dec. 18, 2006 Page 544 of 568 REJ09B0348-0100 Appendix SBY SPC32 SCI3_2 module VCC TXD32 SCINV3 Internal data bus P32 PDR32 PCR32 VSS I2C bus 2 module ICE SCLO SCLI VSS PDR3: Port data register 3 PCR: Port control register 3 Figure B.2 (e) Port 3 Block Diagram (P32) Rev. 1.00 Dec. 18, 2006 Page 545 of 568 REJ09B0348-0100 Appendix SBY SCI3_2 module VCC RE32 RXD32 P31 VSS PCR31 SCINV2 VSS I2C bus 2 module Internal data bus PDR31 PDR3: Port data register 3 PCR3: Port control register 3 ICE SDAO SDAI Figure B.2 (f) Port 3 Block Diagram (P31) Rev. 1.00 Dec. 18, 2006 Page 546 of 568 REJ09B0348-0100 Appendix SBY PUCR30 VCC VCC PMR30 RTC module Internal data bus TMOW P30 PDR30 VSS PCR30 SCI3_2 module SCKIE32 SCKOE32 SCKO32 SCKI32 PDR3: PCR3: PMR3: Port data register 3 Port control register 3 Port mode register 3 PUCR3: Port pull-up control register 3 Figure B.2 (g) Port 3 Block Diagram (P30) Rev. 1.00 Dec. 18, 2006 Page 547 of 568 REJ09B0348-0100 Appendix SBY Timer F module TMOFH SCINV1 VCC SPC31 SCI3_1 module TXD31/IrTXD Internal data bus P42 PDR42 PCR42 VSS PMR42 PDR4: Port data register 4 PCR4: Port contol register 4 PMR4: Port mode register 4 Figure B.3 (a) Port 4 Block Diagram (P42) Rev. 1.00 Dec. 18, 2006 Page 548 of 568 REJ09B0348-0100 Appendix SBY SCI3_1 module VCC PMR41 RE31 RXD31/IrRXD P41 PDR41 VSS Internal data bus PCR41 Timer F module TMOFL PDR4: Port data register 4 PCR4: Port control register 4 PMR4: Port mode register 4 SCINV0 Figure B.3 (b) Port 4 Block Diagram (P41) Rev. 1.00 Dec. 18, 2006 Page 549 of 568 REJ09B0348-0100 Appendix SBY SCI3_1 module VCC SCKIE31 SCKOE31 SCKO31 SCKI31 P40 PDR40 PCR40 VSS PMR40 Internal data bus Timer F module TMIF PDR4: Port data register 4 PCR4: Port control register 4 PMR4: Port mode register 4 Figure B.3 (c) Port 4 Block Diagram (P40) Rev. 1.00 Dec. 18, 2006 Page 550 of 568 REJ09B0348-0100 Appendix SBY PUCR5n VCC VCC PMR5n P5n PDR5n VSS PCR5n Internal data bus WKPn PDR5: PCR5: PMR5: Port data register 5 Port control register 5 Port mode register 5 PUCR5: Port pull-up control register 5 n = 7 to 0 Figure B.4 Port 5 Block Diagram Rev. 1.00 Dec. 18, 2006 Page 551 of 568 REJ09B0348-0100 Appendix SBY PUCR6n VCC Internal data bus Internal data bus VCC PDR6n PCR6n P6n VSS PDR6: PCR6: Port data register 6 Port control register 6 PUCR6: Port pull-up control register 6 n = 7 to 0 Figure B.5 Port 6 Block Diagram SBY VCC PDR7n PCR7n P7n VSS PDR7: Port data register 7 PCR7: Port control register 7 n = 7 to 0 Figure B.6 Port 7 Block Diagram Rev. 1.00 Dec. 18, 2006 Page 552 of 568 REJ09B0348-0100 Appendix SBY VCC Internal data bus PDR8n PCR8n P8n VSS PDR8: Port data register 8 PCR8: Port control register 8 n = 7 to 0 Figure B.7 Port 8 Block Diagram SBY VCC Internal data bus PDR93 PCR93 P93 VSS PDR9: Port data register 9 PCR9: Port control register 9 Figure B.8 (a) Port 9 Block Diagram (P93) Rev. 1.00 Dec. 18, 2006 Page 553 of 568 REJ09B0348-0100 Appendix SBY VCC PMR92 Internal data bus P92 PDR92 VSS PCR92 IRQ4 PDR9: Port data register 9 PCR9: Port control register 9 PMR9: Port mode register 9 Figure B.8 (b) Port 9 Block Diagram (P92) Rev. 1.00 Dec. 18, 2006 Page 554 of 568 REJ09B0348-0100 Appendix SBY PWM module PWMn+1 VCC PMR9n P9n PDR9n VSS PCR9n PDR9: Port data register 9 PCR9: Port control register 9 PMR9: Port mode register 9 n = 1, 0 Figure B.8 (c) Port 9 Block Diagram (P91, P90) SBY VCC PDRAn Internal data bus PCRAn PAn VSS PDRA: Port data register A PCRA: Port control register A n = 3 to 0 Figure B.9 Port A Block Diagram Rev. 1.00 Dec. 18, 2006 Page 555 of 568 REJ09B0348-0100 Internal data bus Appendix PBn Internal data bus A/D module DEC AMR3 to AMR0 VIN n = 7 to 3 Figure B.10 (a) Port B Block Diagram (PB7 to PB3) Rev. 1.00 Dec. 18, 2006 Page 556 of 568 REJ09B0348-0100 Appendix IRQm PMRBn PBn Internal data bus A/D module DEC AMR3 to AMR0 VIN n = 2 to 0 m = 3, 1, 0 Figure B.10 (b) Port B Block Diagram (PB2 to PB0) Rev. 1.00 Dec. 18, 2006 Page 557 of 568 REJ09B0348-0100 Appendix B.2 Port States in Each Operating State Sleep (High-Speed/ MediumActive (High-Speed/ MediumSubsleep Retained Standby High impedance* Retained Retained High impedance* Retained Retained High impedance* Retained Retained High impedance* Retained Retained High impedance* Retained Retained High impedance* Retained Retained High impedance* Retained Retained High impedance* Retained Retained High impedance* High impedance High High High impedance High impedance High impedance Functioning Functioning Retained Functioning Functioning Retained Functioning Functioning Retained Functioning Functioning Retained Functioning Functioning Retained Functioning Functioning Retained Functioning Functioning Retained Functioning Functioning Retained Subactive Functioning Speed) Functioning Watch Retained Port P16 to P10 Reset High impedance Speed) Retained P37, P36, P32 to P30 P42 to P40 High impedance High impedance P57 to P50 High impedance P67 to P60 High impedance P77 to P70 High impedance P87 to P80 High impedance P93 to P90 High impedance PA3 to PA0 High impedance PB7 to PB5, PB4, PB3, PB2 to PB0 High impedance impedance impedance* Notes: * Registers are retained and output level is high impedance. Rev. 1.00 Dec. 18, 2006 Page 558 of 568 REJ09B0348-0100 Appendix C. Product Code Lineup Product Code Regular specifications HD64F38776H4 HD64F38776H10 HD64F38776W4 HD64F38776W10 HD64F38776LP4V HD64F38776LP10V Wide-range specifications HD64F38776H10W HD64F38776W10W HD64F38776LP10WV Masked ROM version Regular specifications HD64338776H HD64338776W HD64338776LPV Wide-range specifications HD64338776HW HD64338776WW HD64338776LPWV Model Marking F38776H4 F38776H10 F38776W4 F38776W10 F38776LP4V F38776LP10V F38776H10 F38776W10 Package (Package Code) 80 pin QFP (FP-80A) 80 pin TQFP (TFP-80C) 80 pin P-TFLGA (TLP-85V) 80 pin QFP (FP-80A) 80 pin TQFP (TFP-80C) Product Classification H8/38776 Flash memory version F38776LP10WV 80 pin P-TFLGA (TLP-85V) 38776(***)H 38776(***)W 38776(***)LPV 38776(***)H 38776(***)W 80 pin QFP (FP-80A) 80 pin TQFP (TFP-80C) 80 pin P-TFLGA (TLP-85V) 80 pin QFP (FP-80A) 80 pin TQFP (TFP-80C) 38776(***)LPWV 80 pin P-TFLGA (TLP-85V) Rev. 1.00 Dec. 18, 2006 Page 559 of 568 REJ09B0348-0100 Appendix Product Classification H8/38775 Masked ROM version Regular specifications Product Code HD64338775H Model Marking 38775(***)H Package (Package Code) 80 pin QFP (FP-80A) 80 pin TQFP (TFP-80C) 80 pin P-TFLGA (TLP-85V) 80 pin QFP (FP-80A) 80 pin TQFP (TFP-80C) 80 pin P-TFLGA (TLP-85V) 80 pin QFP (FP-80A) 80 pin TQFP (TFP-80C) 80 pin P-TFLGA (TLP-85V) 80 pin QFP (FP-80A) 80 pin TQFP (TFP-80C) 80 pin P-TFLGA (TLP-85V) 80 pin QFP (FP-80A) 80 pin TQFP (TFP-80C) 80 pin P-TFLGA (TLP-85V) 80 pin QFP (FP-80A) 80 pin TQFP (TFP-80C) 80 pin P-TFLGA (TLP-85V) HD64338775W 38775(***)W HD64338775LPV 38775(***)LPV Wide-range specifications HD64338775HW 38775(***)H HD64338775WW 38775(***)W HD64338775LPWV 38775(***)LPWV H8/38774 Masked ROM version Regular specifications HD64338774H 38774(***)H HD64338774W 38774(***)W HD64338774LPV 38774(***)LPV Wide-range specifications HD64338774HW 38774(***)H HD64338774WW 38774(***)W HD64338774LPWV 38774(***)LPWV H8/38773 Masked ROM version Regular specifications HD64338773H 38773(***)H HD64338773W 38773(***)W HD64338773LPV 38773(***)LPV Wide-range specifications HD64338773HW 38773(***)H HD64338773WW 38773(***)W HD64338773LPWV 38773(***)LPWV [Legend] (***): ROM code Rev. 1.00 Dec. 18, 2006 Page 560 of 568 REJ09B0348-0100 Appendix D. Package Dimensions The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have priority. Rev. 1.00 Dec. 18, 2006 Page 561 of 568 REJ09B0348-0100 Appendix c1 E *2 HE c 80 21 ZE A1 Figure D.1 Package Dimensions (FP-80A) F A A2 c REJ09B0348-0100 RENESAS Code PRQP0080JB-A Previous Code FP-80A/FP-80AV MASS[Typ.] 1.2g HD *1 JEITA Package Code P-QFP80-14x14-0.65 D NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 41 60 Rev. 1.00 Dec. 18, 2006 Page 562 of 568 40 bp b1 Reference Symbol 61 Dimension in Millimeters Min Nom Max Terminal cross section D E A2 HD 16.9 HE A A1 bp 0.00 0.24 16.9 14 14 2.70 17.2 17.2 17.5 17.5 3.05 0.10 0.32 0.25 0.40 1 20 ZD L L1 b1 c c1 0.12 0.30 0.17 0.15 0.22 Detail F *3 M e 0 0.65 8 e y bp x x y ZD ZE L L1 0.5 0.83 0.83 0.8 1.6 0.12 0.10 1.1 JEITA Package Code P-TQFP80-12x12-0.50 MASS[Typ.] 0.4g RENESAS Code PTQP0080KC-A Previous Code TFP-80C/TFP-80CV HD *1 D 41 60 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 61 40 bp b1 c1 E *2 HE c Reference Symbol Dimension in Millimeters Terminal cross section 21 Min D E Nom 12 12 A2 HD HE 13.8 13.8 A 1.00 14.0 14.0 Max 80 ZE 14.2 14.2 1.20 1 20 Index mark F A A2 ZD c A1 0.00 0.10 0.20 A1 Figure D.2 Package Dimensions (TFP-80C) L L1 *3 bp b1 c 0.17 0.22 0.20 0.12 0.17 0.27 0.22 e y bp x M Detail F c1 0.15 e x y ZD ZE L L1 0 0.5 8 0.10 0.10 1.25 1.25 0.4 0.5 1.0 0.6 Appendix Rev. 1.00 Dec. 18, 2006 Page 563 of 568 REJ09B0348-0100 Appendix JEITA Package Code P-TFLGA85-7x7-0.65 RENESAS Code PTLG0085JA-A Previous Code TLP-85V MASS[Typ.] 0.1g D wSA wSB x4 v y1 S y S e ZD A K J e A S E Reference Symbol Dimension in Millimeters Min Nom 7.0 7.0 0.15 0.20 1.20 Max H G F E D C B A ZE D E B v w A A1 e b x y y1 0.30 0.65 0.35 0.40 0.08 0.10 0.2 SD 1 2 3 4 5 6 b 7 8 9 10 SE ZD ZE 0.575 0.575 xM S A B Figure D.3 Package Dimensions (TLP-85V) Rev. 1.00 Dec. 18, 2006 Page 564 of 568 REJ09B0348-0100 Index Numerics 16-bit timer mode ................................... 220 16-bit timer pulse unit............................. 229 8-bit timer mode ..................................... 221 D Data reading procedure ........................... 209 Data transfer instructions .......................... 29 A A/D converter ......................................... 387 Absolute address....................................... 40 Acknowledge .......................................... 418 Address break ......................................... 443 Addressing modes..................................... 39 Arithmetic operations instructions............ 30 Asynchronous Event Counter (AEC)...... 277 Asynchronous mode ............................... 330 E Effective address....................................... 43 Effective address extension....................... 38 Erase/erase-verify ................................... 146 Erasing units ........................................... 132 Error protection....................................... 148 Exception handling ................................... 55 F Flash memory ......................................... 131 Framing error .......................................... 338 Free-running count operation.................. 249 B Bit manipulation instructions.................... 33 Bit rate .................................................... 319 Bit synchronous circuit ........................... 436 Block data transfer instructions ................ 37 Boot mode .............................................. 139 Boot program.......................................... 138 Branch instructions ................................... 35 Break....................................................... 354 G General registers ....................................... 22 H Hardware protection................................ 148 C Clock pulse generators.............................. 91 Clocked synchronous mode .................... 342 Clocked synchronous serial format......... 427 Condition field.......................................... 38 Condition-code register (CCR)................. 23 Counter operation ................................... 248 CPU .......................................................... 19 I I/O ports .................................................. 155 I2C bus format ......................................... 417 I2C bus interface 2 (IIC2)........................ 401 Immediate ................................................. 41 Initial setting procedure .......................... 208 Input capture function ............................. 251 Input capture signal timing ..................... 265 Instruction set............................................ 28 Rev. 1.00 Dec. 18, 2006 Page 565 of 568 REJ09B0348-0100 Interrupt mask bit (I)................................. 23 IrDA........................................................ 348 Programming/ erasing in user program mode................. 141 L Large current ports...................................... 5 Logic operations instructions.................... 32 R RAM ....................................................... 153 Realtime clock (RTC) ............................. 199 Register direct ........................................... 39 Register field............................................. 38 Register indirect........................................ 40 Register indirect with displacement.......... 40 Register indirect with post-increment ....... 40 Register indirect with pre-decrement........ 40 Registers ABRKCR2.................. 444, 451, 457, 462 ABRKSR2 .................. 446, 451, 457, 462 ADRR ......................... 389, 453, 458, 464 ADSR.......................... 391, 453, 458, 464 AEGSR ....................... 282, 452, 457, 463 AMR ........................... 390, 453, 458, 464 BAR2H ....................... 446, 452, 457, 462 BAR2L........................ 446, 452, 457, 462 BDR2H ....................... 446, 452, 457, 462 BDR2L........................ 446, 452, 457, 462 BRR ............................ 319, 452, 457, 463 CKSTPR1 ................... 111, 454, 460, 465 CKSTPR2 ................... 111, 454, 460, 465 EBR1........................... 136, 450, 455, 461 ECCR.......................... 283, 452, 457, 463 ECCSR........................ 284, 452, 457, 463 ECH ............................ 286, 452, 457, 463 ECL............................. 286, 452, 457, 463 ECPWCR.................... 280, 452, 457, 462 ECPWDR.................... 281, 452, 457, 462 FENR .......................... 137, 450, 455, 461 FLMCR1..................... 134, 450, 455, 461 FLMCR2..................... 135, 450, 455, 461 FLPWCR .................... 137, 450, 455, 461 ICCR1 ......................... 404, 451, 456, 462 ICCR2 ......................... 407, 451, 456, 462 M Mark state ............................................... 354 Memory indirect ....................................... 41 Memory map ............................................ 20 Module standby function ........................ 127 N Noise canceler ........................................ 430 O On-board programming modes............... 138 Operation field.......................................... 38 Output compare output timing................ 264 Overrun error .......................................... 338 P Parity error.............................................. 338 Periodic count operation......................... 249 Pin assignment............................................ 8 Power-down modes ................................ 107 Power-down states.................................. 149 Power-on reset circuit............................. 439 Program counter (PC)............................... 23 Program/program-verify......................... 143 Program-counter relative .......................... 41 Programmer mode .................................. 149 Programming units ................................. 132 Rev. 1.00 Dec. 18, 2006 Page 566 of 568 REJ09B0348-0100 ICDRR........................ 416, 451, 456, 462 ICDRS ................................................ 416 ICDRT ........................ 416, 451, 456, 462 ICIER.......................... 411, 451, 456, 462 ICMR.......................... 409, 451, 456, 462 ICSR ........................... 413, 451, 456, 462 IEGR............................. 69, 454, 459, 465 IENR............................. 71, 454, 459, 465 INTM............................ 79, 454, 459, 465 IPR................................ 78, 451, 456, 462 IrCR ............................ 329, 452, 457, 463 IRR ............................... 73, 454, 459, 465 IWPR ............................ 76, 454, 460, 465 OCR............................ 216, 453, 458, 463 OSCCR ......................... 94, 453, 458, 464 PCR1........................... 156, 454, 459, 464 PCR3........................... 165, 454, 459, 465 PCR4........................... 170, 454, 459, 465 PCR5........................... 174, 454, 459, 465 PCR6........................... 178, 454, 459, 465 PCR7........................... 182, 454, 459, 465 PCR8........................... 184, 454, 459, 465 PCR9........................... 187, 454, 459, 465 PCRA.......................... 190, 454, 459, 465 PDR1 .......................... 156, 453, 459, 464 PDR3 .......................... 164, 453, 459, 464 PDR4 .......................... 169, 453, 459, 464 PDR5 .......................... 174, 453, 459, 464 PDR6 .......................... 178, 453, 459, 464 PDR7 .......................... 181, 454, 459, 464 PDR8 .......................... 184, 454, 459, 464 PDR9 .......................... 186, 454, 459, 464 PDRA ......................... 189, 454, 459, 464 PDRB.......................... 192, 454, 459, 464 PMR1.......................... 157, 453, 458, 464 PMR3.......................... 166, 453, 458, 464 PMR4.......................... 171, 453, 458, 464 PMR5.......................... 175, 453, 458, 464 PMR9.......................... 187, 453, 458, 464 PMRB ......................... 193, 453, 458, 464 PUCR1 ........................ 157, 454, 459, 464 PUCR3 ........................ 165, 454, 459, 464 PUCR5 ........................ 175, 454, 459, 464 PUCR6 ........................ 179, 454, 459, 464 PWCR ......................... 380, 453, 458, 464 PWDR......................... 381, 453, 458, 464 RDR ............................ 310, 452, 457, 463 RHRDR....................... 202, 451, 456, 462 RMINDR .................... 201, 451, 456, 462 RSECDR..................... 201, 451, 456, 462 RSR..................................................... 310 RTCCR1 ..................... 204, 451, 456, 462 RTCCR2 ..................... 205, 451, 456, 462 RTCCSR ..................... 206, 451, 456, 462 RTCFLG ..................... 207, 451, 456, 462 RWKDR...................... 203, 451, 456, 462 SAR............................. 415, 451, 456, 462 SCR3........................... 314, 452, 457, 463 SCR4........................... 361, 450, 455, 461 SCSR4......................... 364, 450, 455, 461 SMR ............................ 311, 452, 457, 463 SPCR........................... 327, 452, 457, 463 SSR ............................. 316, 452, 457, 463 SUB32CR ..................... 93, 451, 456, 462 SYSCR1...................... 108, 454, 459, 465 TC ............................... 215, 453, 458, 463 TCNT .......................... 243, 450, 455, 461 TCR............................. 233, 450, 455, 461 TCRF .......................... 217, 453, 458, 463 TCSRF ........................ 218, 453, 458, 463 TCSRWD.................... 295, 453, 458, 463 TCWD......................... 299, 453, 458, 463 TDR ............................ 310, 452, 457, 463 TGR ............................ 243, 450, 455, 461 TIER............................ 241, 450, 455, 461 TIOR ........................... 236, 450, 455, 461 TMDR......................... 235, 450, 455, 461 TMWD........................ 299, 452, 458, 463 TSR ............................. 242, 450, 455, 461 TSTR........................... 244, 450, 455, 461 Rev. 1.00 Dec. 18, 2006 Page 567 of 568 REJ09B0348-0100 TSYR...........................245, 450, 455, 461 WEGR ...........................70, 452, 457, 463 ROM....................................................... 131 System clock generator ............................. 95 System control instructions....................... 36 S Serial communication interface 3 ........... 305 Serial communication interface 4 ........... 359 Shift instructions....................................... 32 Slave address .......................................... 418 Sleep mode ............................................. 119 Software protection................................. 148 Stack pointer (SP)..................................... 22 Standby mode ......................................... 119 Start condition ........................................ 418 Stop condition......................................... 418 Subactive mode ...................................... 121 Subclock generator ................................... 97 Subsleep mode........................................ 120 Synchronous operation ........................... 253 T TCNT count timing................................. 263 Timer F ................................................... 213 Toggle output.......................................... 250 Transfer rate............................................ 406 V Vector address........................................... 56 W Watchdog timer....................................... 293 Waveform output by compare match...... 250 Rev. 1.00 Dec. 18, 2006 Page 568 of 568 REJ09B0348-0100 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/38776 Group Publication Date: Rev.1.00, Dec. 18, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.0 H8/38776 Group Hardware Manual |
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